Module and signal names can collide in illegal ways in generated SystemVerilog

[mkorbel1]

Describe the bug

It is possible to name a signal and a module instance the same thing, but in generated SystemVerilog they cannot be the same. They should be uniquified.

To Reproduce

Create a signal name and module instance name that are the same and generate SystemVerilog

Expected behavior

Names are properly uniquified so that generated SystemVerilog is valid

Actual behavior

Invalid SystemVerilog is generated, leading to a compile time error

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

In a fix, it's important to consider every combination of:

• input name
• output name
• internal signal name
• module definition name
• module instance name