[issue#137]: Add mechanism for reset all flop of Sequential

lib/src/modules/conditional.dart

@@ -20,7 +20,7 @@ import 'package:rohd/src/utilities/uniquifier.dart';
 /// Represents a block of logic, similar to `always` blocks in SystemVerilog.
 abstract class _Always extends Module with CustomSystemVerilog {
   /// A [List] of the [Conditional]s to execute.
-  final List<Conditional> conditionals;
+  late final List<Conditional> conditionals;
 
   /// A mapping from internal receiver signals to designated [Module] outputs.
   final Map<Logic, Logic> _assignedReceiverToOutputMap = {};
@@ -30,9 +30,41 @@ abstract class _Always extends Module with CustomSystemVerilog {
 
   final Uniquifier _portUniquifier = Uniquifier();
 
-  _Always(this.conditionals, {super.name = 'always'}) {
+  /// Accepts [conditionals] and set maps receivers to output
+  ///
+  /// If [reset] is set then For a receiver assign default reset value
+  /// as `0` unless a reset value for is present [resetValues]
+  _Always(List<Conditional> conditionals,
+      {Logic? reset, Map<Logic, dynamic>? resetValues, super.name = 'always'}) {
     // create a registration of all inputs and outputs of this module
     var idx = 0;
+
+    // Get all Receivers
+    final allReceivers =
+        conditionals.map((e) => e.getReceivers()).expand((e) => e).toList();
+
+    // This will reset the conditionals on setting the `reset` flag
+    if (reset != null) {
+      conditionals = [
+        If(
+          reset,
+          then: [
+            ...allReceivers.map((rec) {
+              final driver = resetValues?[rec] ?? 0;
+              return rec < driver;
+              // If resetValue for a receiver is defined,
+              // then use it for assigning receiver
+              // else assign zero as resetValue
+            })
+          ],
+          orElse: conditionals,
+        ),
+      ];
+    }
+
+    // ignore: prefer_initializing_formals
+    this.conditionals = conditionals;
+
     for (final conditional in conditionals) {
       for (final driver in conditional.getDrivers()) {
         if (!_assignedDriverToInputMap.containsKey(driver)) {
@@ -267,15 +299,23 @@ class Sequential extends _Always {
   /// The input clocks used in this block.
   final List<Logic> _clks = [];
 
+  /// This sets the Sequential conditions to reset
+  // ignore: overridden_fields
+  Logic? reset;
+
+  /// This sets a particular Sequential conditions receiver to resetValues
+  Map<Logic, dynamic>? resetValues = {};
+
   /// Constructs a [Sequential] single-triggered by [clk].
   Sequential(Logic clk, List<Conditional> conditionals,
-      {String name = 'sequential'})
-      : this.multi([clk], conditionals, name: name);
+      {Logic? reset, String name = 'sequential'})
+      : this.multi([clk], conditionals, name: name, reset: reset);
 
   /// Constructs a [Sequential] multi-triggered by any of [clks].
   Sequential.multi(List<Logic> clks, List<Conditional> conditionals,
-      {String name = 'sequential'})
-      : super(conditionals, name: name) {
+      {this.reset, this.resetValues, String name = 'sequential'})
+      : super(conditionals,
+            name: name, reset: reset, resetValues: resetValues) {
     for (var i = 0; i < clks.length; i++) {
       final clk = clks[i];
       if (clk.width > 1) {

test/conditionals_test.dart

@@ -13,6 +13,35 @@ import 'package:rohd/src/exceptions/sim_compare/sim_compare_exceptions.dart';
 import 'package:rohd/src/utilities/simcompare.dart';
 import 'package:test/test.dart';
 
+import 'counter_wintf_test.dart';
+
+class ResetFlipflops extends Module {
+  late final CounterInterface intf;
+  ResetFlipflops(CounterInterface intf) : super(name: 'shorthandmodule') {
+    this.intf = CounterInterface(intf.width)
+      ..connectIO(this, intf,
+          inputTags: {CounterDirection.inward},
+          outputTags: {CounterDirection.outward});
+
+    // this should do nothing
+    this.intf.connectIO(this, intf);
+
+    _buildLogic();
+  }
+  void _buildLogic() {
+    final nextVal = Logic(name: 'nextVal', width: intf.width);
+
+    nextVal <= intf.val + 1;
+
+    Sequential(
+        SimpleClockGenerator(10).clk,
+        [
+          If(intf.en, then: [intf.val < nextVal])
+        ],
+        reset: intf.reset);
+  }
+}
+
 class ShorthandAssignModule extends Module {
   ShorthandAssignModule(
       Logic preIncr, Logic preDecr, Logic mulAssign, Logic divAssign, Logic b)
@@ -594,4 +623,25 @@ void main() {
     final simResult = SimCompare.iverilogVector(mod, vectors);
     expect(simResult, equals(true));
   });
+
+  test('resetFlipflop', () async {
+    final mod = ResetFlipflops(CounterInterface(8));
+    await mod.build();
+    final vectors = [
+      Vector({'en': 0, 'reset': 1}, {}),
+      Vector({'en': 0, 'reset': 1}, {'val': 0}),
+      Vector({'en': 1, 'reset': 1}, {'val': 0}),
+      Vector({'en': 1, 'reset': 0}, {'val': 0}),
+      Vector({'en': 1, 'reset': 0}, {'val': 1}),
+      Vector({'en': 1, 'reset': 0}, {'val': 2}),
+      Vector({'en': 1, 'reset': 0}, {'val': 3}),
+      Vector({'en': 0, 'reset': 0}, {'val': 4}),
+      Vector({'en': 0, 'reset': 0}, {'val': 4}),
+      Vector({'en': 1, 'reset': 0}, {'val': 4}),
+      Vector({'en': 0, 'reset': 0}, {'val': 5}),
+    ];
+    await SimCompare.checkFunctionalVector(mod, vectors);
+    final simResult = SimCompare.iverilogVector(mod, vectors);
+    expect(simResult, equals(true));
+  });
 }