[issue#137]: Add mechanism for reset all flop of Sequential

lib/src/modules/conditional.dart

@@ -23,7 +23,9 @@ import 'package:rohd/src/utilities/uniquifier.dart';
 /// Represents a block of logic, similar to `always` blocks in SystemVerilog.
 abstract class _Always extends Module with CustomSystemVerilog {
   /// A [List] of the [Conditional]s to execute.
-  final List<Conditional> conditionals;
+  List<Conditional> get conditionals =>
+      UnmodifiableListView<Conditional>(_conditionals);
+  late List<Conditional> _conditionals;
 
   /// A mapping from internal receiver signals to designated [Module] outputs.
   final Map<Logic, Logic> _assignedReceiverToOutputMap =
@@ -34,9 +36,43 @@ abstract class _Always extends Module with CustomSystemVerilog {
 
   final Uniquifier _portUniquifier = Uniquifier();
 
-  _Always(this.conditionals, {super.name = 'always'}) {
+  /// Executes provided [conditionals] at the appropriate time (specified by
+  /// child class).
+  ///
+  /// If [reset] is provided, then all signals driven by this block will be
+  /// conditionally reset when the signal is high.
+  /// The default reset value is to `0`, but if [resetValues] is provided then
+  /// the corresponding value
+  /// associated with the driven signal will be set to that value instead upon
+  /// reset.
+  _Always(this._conditionals,
+      {Logic? reset, Map<Logic, dynamic>? resetValues, super.name = 'always'}) {
     // create a registration of all inputs and outputs of this module
     var idx = 0;
+
+    // Get all Receivers
+    final allReceivers =
+        conditionals.map((e) => e.receivers).expand((e) => e).toList();
+
+    // This will reset the conditionals on setting the `reset` flag
+    if (reset != null) {
+      _conditionals = [
+        // If resetValue for a receiver is defined,
+        If(
+          reset,
+          // then use it for assigning receiver
+          then: [
+            ...allReceivers.map((rec) {
+              final driver = resetValues?[rec] ?? 0;
+              return rec < driver;
+            })
+          ],
+          // else assign zero as resetValue
+          orElse: conditionals,
+        ),
+      ];
+    }
+
     for (final conditional in conditionals) {
       for (final driver in conditional.drivers) {
         if (!_assignedDriverToInputMap.containsKey(driver)) {
@@ -309,13 +345,15 @@ class Sequential extends _Always {
 
   /// Constructs a [Sequential] single-triggered by [clk].
   Sequential(Logic clk, List<Conditional> conditionals,
-      {String name = 'sequential'})
-      : this.multi([clk], conditionals, name: name);
+      {Logic? reset,
+      Map<Logic, dynamic>? resetValues,
+      String name = 'sequential'})
+      : this.multi([clk], conditionals,
+            name: name, reset: reset, resetValues: resetValues);
 
   /// Constructs a [Sequential] multi-triggered by any of [clks].
-  Sequential.multi(List<Logic> clks, List<Conditional> conditionals,
-      {String name = 'sequential'})
-      : super(conditionals, name: name) {
+  Sequential.multi(List<Logic> clks, super.conditionals,
+      {super.reset, super.resetValues, super.name = 'sequential'}) {
     for (var i = 0; i < clks.length; i++) {
       final clk = clks[i];
       if (clk.width > 1) {

test/counter_wintf_test.dart

@@ -7,6 +7,7 @@
 /// 2021 May 25
 /// Author: Max Korbel <max.korbel@intel.com>
 ///
+
 import 'package:rohd/rohd.dart';
 import 'package:rohd/src/utilities/simcompare.dart';
 import 'package:test/test.dart';
@@ -17,6 +18,7 @@ class CounterInterface extends Interface<CounterDirection> {
   Logic get en => port('en');
   Logic get reset => port('reset');
   Logic get val => port('val');
+  Logic get resetVal => port('resetVal');
 
   final int width;
   CounterInterface(this.width) {
@@ -32,7 +34,8 @@ class CounterInterface extends Interface<CounterDirection> {
 
 class Counter extends Module {
   late final CounterInterface intf;
-  Counter(CounterInterface intf) {
+  Counter(CounterInterface intf,
+      {bool useBuiltInSequentialReset = false, int resetValue = 0}) {
     this.intf = CounterInterface(intf.width)
       ..connectIO(this, intf,
           inputTags: {CounterDirection.inward},
@@ -41,14 +44,27 @@ class Counter extends Module {
     // this should do nothing
     this.intf.connectIO(this, intf);
 
-    _buildLogic();
-  }
-
-  void _buildLogic() {
     final nextVal = Logic(name: 'nextVal', width: intf.width);
-
     nextVal <= intf.val + 1;
 
+    if (useBuiltInSequentialReset) {
+      _buildResetValLogic(nextVal, resetValue: resetValue);
+    } else {
+      _buildLogic(nextVal);
+    }
+  }
+  void _buildResetValLogic(Logic nextVal, {int resetValue = 0}) {
+    final resetValues = <Logic, Logic>{intf.val: Const(resetValue, width: 8)};
+    Sequential(
+        SimpleClockGenerator(10).clk,
+        [
+          If(intf.en, then: [intf.val < nextVal])
+        ],
+        reset: intf.reset,
+        resetValues: resetValues);
+  }
+
+  void _buildLogic(Logic nextVal) {
     Sequential(SimpleClockGenerator(10).clk, [
       If(intf.reset, then: [
         intf.val < 0
@@ -59,6 +75,27 @@ class Counter extends Module {
   }
 }
 
+Future<void> moduleTest(Counter mod) async {
+  await mod.build();
+  final vectors = [
+    Vector({'en': 0, 'reset': 1}, {}),
+    Vector({'en': 0, 'reset': 1}, {'val': 0}),
+    Vector({'en': 1, 'reset': 1}, {'val': 0}),
+    Vector({'en': 1, 'reset': 0}, {'val': 0}),
+    Vector({'en': 1, 'reset': 0}, {'val': 1}),
+    Vector({'en': 1, 'reset': 0}, {'val': 2}),
+    Vector({'en': 1, 'reset': 0}, {'val': 3}),
+    Vector({'en': 0, 'reset': 0}, {'val': 4}),
+    Vector({'en': 0, 'reset': 0}, {'val': 4}),
+    Vector({'en': 1, 'reset': 0}, {'val': 4}),
+    Vector({'en': 0, 'reset': 0}, {'val': 5}),
+    Vector({'en': 0, 'reset': 0}, {'val': 5}),
+  ];
+  await SimCompare.checkFunctionalVector(mod, vectors);
+  final simResult = SimCompare.iverilogVector(mod, vectors);
+  expect(simResult, equals(true));
+}
+
 void main() {
   tearDown(() async {
     await Simulator.reset();
@@ -67,23 +104,34 @@ void main() {
   group('simcompare', () {
     test('counter', () async {
       final mod = Counter(CounterInterface(8));
-      await mod.build();
-      final vectors = [
-        Vector({'en': 0, 'reset': 1}, {}),
-        Vector({'en': 0, 'reset': 1}, {'val': 0}),
-        Vector({'en': 1, 'reset': 1}, {'val': 0}),
-        Vector({'en': 1, 'reset': 0}, {'val': 0}),
-        Vector({'en': 1, 'reset': 0}, {'val': 1}),
-        Vector({'en': 1, 'reset': 0}, {'val': 2}),
-        Vector({'en': 1, 'reset': 0}, {'val': 3}),
-        Vector({'en': 0, 'reset': 0}, {'val': 4}),
-        Vector({'en': 0, 'reset': 0}, {'val': 4}),
-        Vector({'en': 1, 'reset': 0}, {'val': 4}),
-        Vector({'en': 0, 'reset': 0}, {'val': 5}),
-      ];
-      await SimCompare.checkFunctionalVector(mod, vectors);
-      final simResult = SimCompare.iverilogVector(mod, vectors);
-      expect(simResult, equals(true));
+      await moduleTest(mod);
     });
   });
+  test('resetFlipflop from root w/o resetVal', () async {
+    final mod = Counter(CounterInterface(8), useBuiltInSequentialReset: true);
+    await moduleTest(mod);
+  });
+
+  test('resetFlipflop from root w/ resetVal', () async {
+    final mod = Counter(CounterInterface(8),
+        useBuiltInSequentialReset: true, resetValue: 3);
+    await mod.build();
+    final vectors = [
+      Vector({'en': 0, 'reset': 1}, {}),
+      Vector({'en': 0, 'reset': 1}, {'val': 3}),
+      Vector({'en': 1, 'reset': 1}, {'val': 3}),
+      Vector({'en': 1, 'reset': 0}, {'val': 3}),
+      Vector({'en': 1, 'reset': 0}, {'val': 4}),
+      Vector({'en': 1, 'reset': 0}, {'val': 5}),
+      Vector({'en': 1, 'reset': 0}, {'val': 6}),
+      Vector({'en': 0, 'reset': 0}, {'val': 7}),
+      Vector({'en': 0, 'reset': 0}, {'val': 7}),
+      Vector({'en': 1, 'reset': 0}, {'val': 7}),
+      Vector({'en': 0, 'reset': 0}, {'val': 8}),
+      Vector({'en': 0, 'reset': 0}, {'val': 8}),
+    ];
+    await SimCompare.checkFunctionalVector(mod, vectors);
+    final simResult = SimCompare.iverilogVector(mod, vectors);
+    expect(simResult, equals(true));
+  });
 }