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pointwise_wide_handshake.bmp |
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return {} |
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return {} |
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local types = require "types" | ||
local C = require "examplescommon" | ||
local R = require "rigel" | ||
local harness = require "harnessSOC" | ||
local Zynq = require "zynq" | ||
local SOC = require "soc" | ||
local SDF = require "sdf" | ||
local G = require "generators" | ||
local RM = require "modules" | ||
local AXI = require "axi" | ||
import "state" | ||
|
||
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--function FlowControl(readFn) | ||
-- return | ||
--end | ||
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noc = Zynq.SimpleNOC():instantiate("ZynqNOC") | ||
noc.extern=true | ||
local regs = SOC.axiRegs({},SDF{1,128*64},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs") | ||
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print("INST",noc.read) | ||
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-- only issue requests for which we have pre-allocated storage | ||
state FlowControl(I:AXI.ReadAddress64,O:AXI.ReadData64) | ||
fifo:RM.fifo(AXI.ReadDataTuple(64),8,nil,nil,nil,nil,nil,true,nil,true) | ||
--1 | ||
while R.c(true,types.bool()) do | ||
if G.LT{7}(fifo:size()) then | ||
[fifo:store(noc.read(I))] | ||
else | ||
[C.Stall(AXI.ReadAddressTuple,true)(I)] | ||
[fifo:store(noc:read(C.Invalid(AXI.ReadAddressTuple,true)()))] | ||
end | ||
yield fifo:load() -- 2 | ||
end | ||
end | ||
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--l-ocal FC = FlowControl(noc.read) | ||
--print(FlowControl) | ||
--print(FlowControl:toVerilog()) | ||
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harness({regs.start, G.AXIReadBurst{ "frame_128.raw", {128,64}, types.u(8), 0, FlowControl }, G.HS{G.Map{G.Add{200}}}, G.AXIWriteBurst{"out/state_flowcontrol",noc.write}, regs.done},nil,{regs}) |
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local types = require "types" | ||
local C = require "examplescommon" | ||
local R = require "rigel" | ||
local harness = require "harnessSOC" | ||
local Zynq = require "zynq" | ||
local SOC = require "soc" | ||
local SDF = require "sdf" | ||
local G = require "generators" | ||
import "state" | ||
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state StateExample(I:types.uint(8),O:types.uint(8)) | ||
--1 | ||
--yield R.c(8,types.u8) | ||
while R.c("mytrue",true,types.bool()) do | ||
if C.GTConst(types.uint(8),16)(I) then | ||
yield R.c(255,types.u8) --2 | ||
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if C.GTConst(types.uint(8),128)(I) then | ||
yield R.c(128,types.u8) --3 | ||
else | ||
yield R.c(64,types.u8) --4 | ||
end | ||
else | ||
yield R.c(0,types.u8) --5 | ||
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if C.GTConst(types.uint(8),8)(I) then | ||
yield R.c(16,types.u8) --6 | ||
else | ||
yield R.c(8,types.u8) --7 | ||
end | ||
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end | ||
end | ||
end | ||
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--print("COUNTER",StateExample) | ||
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--print("counter",StateExample:toVerilog()) | ||
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noc = Zynq.SimpleNOC():instantiate("ZynqNOC") | ||
noc.extern=true | ||
local regs = SOC.axiRegs({},SDF{1,128*64},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs") | ||
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harness({regs.start, G.AXIReadBurst{ "frame_128.raw", {128,64}, types.u(8), 0, noc.read }, G.Map{G.HS{StateExample}}, G.Map{G.FIFO{128}}, G.AXIWriteBurst{"out/state_simple",noc.write}, regs.done},nil,{regs}) | ||
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--harness({regs.start, G.AXIReadBurst{ "frame_128.raw", {128,64}, types.u(8), 0, noc.read }, G.Map{G.HS{C.plusConst(types.u8,0)}}, G.AXIWriteBurst{"out/stateex",noc.write}, regs.done},nil,{regs}) |
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