Nocexample (#145)

Fixed slave interface wiring to make sense. Added support for AXI IDs in TB. TB fixes. Added pulpino NOC example.

.circleci/config.yml

@@ -47,6 +47,15 @@ jobs:
       - run: sudo apt-get install luajit verilator
       - run: cd examples; make bjump
       - run: test -e examples/out/bjump_done.txt || exit      
+  pulpino:
+    docker:
+      - image: circleci/python:3.7.1
+    steps:
+      - checkout
+      - run: git submodule update --init --recursive
+      - run: sudo apt-get install luajit verilator
+      - run: cd examples; make pulpino
+      - run: test -e examples/out/pulpino_done.txt || exit      
   unit:
     docker:
       - image: circleci/python:3.7.1
@@ -93,3 +102,4 @@ workflows:
       - terra
       - bjump
       - state
+      - pulpino

.gitmodules

@@ -2,8 +2,14 @@
 	path = modules/bsg_ip_cores
 	url = https://bitbucket.org/taylor-bsg/bsg_ip_cores.git
 [submodule "modules/axi_node"]
-	path = modules/axi_node
+	path = modules/pulpino/axi_node
 	url = https://github.com/pulp-platform/axi_node.git
 [submodule "modules/axi_size_conv"]
-	path = modules/axi_size_conv
+	path = modules/pulpino/axi_size_conv
 	url = https://github.com/pulp-platform/axi_size_conv.git
+[submodule "modules/axi"]
+	path = modules/pulpino/axi
+	url = https://github.com/pulp-platform/axi.git
+[submodule "modules/pulpino/common_cells"]
+	path = modules/pulpino/common_cells
+	url = https://github.com/pulp-platform/common_cells.git

examples/gold/soc_convgenTaps.regout.lua

@@ -1 +1 @@
-return {regs_coeffs=4}
+return {InstCall_regs_coeffs=4}

examples/gold/soc_pulpino_noc.regout.lua

@@ -0,0 +1 @@
+return {}

examples/gold/soc_pulpino_noc.verilatorSOC.cycles.txt

@@ -0,0 +1 @@
+1515

examples/gold/soc_readlen.regout.lua

@@ -1 +1 @@
-return {regs_readAddress=805339136,regs_len=1024,regs_writeAddress=805347328}
+return {InstCall_regs_readAddress=805339136,InstCall_regs_len=1024,InstCall_regs_writeAddress=805347328}

examples/gold/soc_regin.regout.lua

@@ -1 +1 @@
-return {regs_offset=200}
+return {InstCall_regs_offset=200}

examples/gold/soc_regout.regout.lua

@@ -1 +1 @@
-return {regs_lastPx=33,regs_offset=200}
+return {InstCall_regs_lastPx=33,InstCall_regs_offset=200}

examples/gold/soc_simple_uniform.regout.lua

@@ -1 +1 @@
-return {regs_readAddress=805339136,regs_writeAddress=805347328}
+return {InstCall_regs_readAddress=805339136,InstCall_regs_writeAddress=805347328}

examples/gold/soc_tokencounter.regout.lua

@@ -1 +1 @@
-return {regs_startCnt=16384,regs_endCnt=4096}
+return {InstCall_regs_startCnt=16384,InstCall_regs_endCnt=4096}

examples/makefile

@@ -10,7 +10,8 @@ VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.correct.txt,$(SRCS_
 VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.regcorrect.txt,$(SRCS_SOC))	
 VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.cyclescorrect.txt,$(SRCS_SOC))
 
-SRCS_STATE = state_simple.t state_flowcontrol.t
+# state_flowcontrol.t
+SRCS_STATE = state_simple.t
 
 STATE = $(patsubst %.t,$(BUILDDIR)/%.verilatorSOC.bit,$(SRCS_STATE))
 STATE += $(patsubst %.t,$(BUILDDIR)/%.verilatorSOC.raw,$(SRCS_STATE))

examples/soc_15x15.lua

@@ -10,9 +10,9 @@ local types = require "types"
 local SDF = require "sdf"
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+regs = SOC.axiRegs({},SDF{1,256}):instantiate("regs")
+noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-regs = SOC.axiRegs({},SDF{1,256},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 ------------
 inp = R.input( types.uint(8) )

examples/soc_15x15x15.lua

@@ -10,9 +10,9 @@ local types = require "types"
 local SDF = require "sdf"
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+regs = SOC.axiRegs({},SDF{1,240}):instantiate("regs")
+noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-regs = SOC.axiRegs({},SDF{1,240},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 ------------
 inp = R.input( types.uint(8) )

examples/soc_2in.lua

@@ -9,9 +9,10 @@ require "types".export()
 local SDF = require "sdf"
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC(2):instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,1024}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(2,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-regs = SOC.axiRegs({},SDF{1,1024},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate()
 
 local inp = R.input(R.HandshakeTrigger)
 local inp0, inp1 = RS.fanOut{input=inp,branches=2}

examples/soc_arbiter.lua

@@ -9,9 +9,9 @@ local SDF = require "sdf"
 types.export()
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,1024}):instantiate("regs")
+local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-local regs = SOC.axiRegs({},SDF{1,1024},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 local OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,
   function(i)
@@ -23,5 +23,4 @@ local OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,
     return G.AXIWriteBurstSeq{"out/soc_arbiter",{64,64},8,noc.write}(arb)
   end}
 
-
 harness({regs.start, OffsetModule, regs.done},nil,{regs})

examples/soc_bjump_cache.lua

@@ -19,9 +19,11 @@ local bjump = require "bjump"
 local NOCACHE = string.find(arg[0],"nocache")
 
 local W,H = 128,64
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,W*H*8*8}):instantiate("regs")
+
+noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-local regs = SOC.axiRegs({},SDF{1,W*H*8*8},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
+
 
 local PosToAddr = G.Module{"PosToAddr",ar(u16,2),
   function(loc)

examples/soc_convgen.lua

@@ -12,12 +12,13 @@ local Zynq = require "zynq"
 local ConvWidth = 4
 local ConvRadius = ConvWidth/2
 
-inSize = { 1920, 1080 }
-padSize = { 1920+16, 1080+3 }
+local inSize = { 1920, 1080 }
+local padSize = { 1920+16, 1080+3 }
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,padSize[1]*padSize[2]}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-regs = SOC.axiRegs({},SDF{1,padSize[1]*padSize[2]},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 local conv = Module{ ar(u(8),ConvWidth,ConvWidth),
 function(inp)

examples/soc_convgenTaps.lua

@@ -12,18 +12,19 @@ local Zynq = require "zynq"
 local ConvWidth = 4
 local ConvRadius = ConvWidth/2
 
-inSize = { 1920, 1080 }
-padSize = { 1920+16, 1080+3 }
+local inSize = { 1920, 1080 }
+local padSize = { 1920+16, 1080+3 }
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
-noc.extern=true
-
-regs = SOC.axiRegs({
+local regs = SOC.axiRegs({
   coeffs={ar(u(32),ConvWidth,ConvWidth),
           {4, 14, 14,  4,
            14, 32, 32, 14,
            14, 32, 32, 14,
-           4, 14, 14,  4}}},SDF{1,padSize[1]*padSize[2]},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
+           4, 14, 14,  4}}},SDF{1,padSize[1]*padSize[2]}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
+noc.extern=true
+
 
 local conv = Module{ ar(u(8),ConvWidth,ConvWidth),
 function(inp)

examples/soc_convtest.lua

@@ -8,9 +8,10 @@ require "types".export()
 local SDF = require "sdf"
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,8192}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-local regs = SOC.axiRegs({},SDF{1,8192},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 ConvTop = G.Module{
   function(i)

examples/soc_filterseq.lua

@@ -9,9 +9,10 @@ types.export()
 local SDF = require "sdf"
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,128*64}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-local regs = SOC.axiRegs({},SDF{1,128*64},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 local OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,
   function(i)

examples/soc_filterseq8.lua

@@ -11,9 +11,10 @@ local J = require "common"
 types.export()
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,1024}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-local regs = SOC.axiRegs({},SDF{1,1024},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 IdxGT = G.Module{"IdxGT",function(i) return G.GT(i[0][1],i[1][1]) end}
 

examples/soc_flip.lua

@@ -8,13 +8,14 @@ local SDF = require "sdf"
 local Zynq = require "zynq"
 require "types".export()
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,1024}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-regs = SOC.axiRegs({},SDF{1,1024},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 local W,H = 128,64
 
-addrGen = Module{function(inp)
+addrGen = Module{SDF{1,1},function(inp)
   local x, y = Index{0}(Index{0}(inp)), Index{1}(Index{0}(inp))
   local resx = AddMSBs{16}(x)
   local resy = Mul( Sub(c(H-1,u(32)),AddMSBs{16}(y)),c(W/8,u(32)) )

examples/soc_flipWrite.lua

@@ -8,13 +8,14 @@ local SDF = require "sdf"
 require "types".export()
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,1024}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-regs = SOC.axiRegs({},SDF{1,1024},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 local W,H = 128,64
 
-AddrGen = Module{function(inp)
+AddrGen = Module{SDF{1,1},function(inp)
   local x, y = Index{0}(Index{0}(inp)), Index{1}(Index{0}(inp))
   local resx = AddMSBs{16}(x)
   local resy = Mul( Sub(c(H-1,u(32)),AddMSBs{16}(y)),c(W/8,u(32)) )

examples/soc_parread.lua

@@ -10,9 +10,10 @@ local SDF = require "sdf"
 types.export()
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC(2):instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,(128*64)/16}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(2,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-local regs = SOC.axiRegs({},SDF{1,(128*64)/16},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate()
 
 -- this will use 2 AXI ports to read in parallel at twice the BW
 

examples/soc_pulpino_noc.lua

@@ -9,36 +9,57 @@ local G = require "generators"
 local types = require "types"
 local harness = require "harnessSOC"
 
-zynqNOC = Zynq.SimpleNOC():instantiate("ZynqNOC")
+
+-- axiRegs expects 32 bit port
+local regs = SOC.axiRegs( {}, SDF{1,(128*64)/8} ):instantiate("regs")
+--local regs_read_32 = Pulpino.AXIReadBusResize(regs.read,64,32)
+--local regs_write_32 = Pulpino.AXIWriteBusResize(regs.write,64,32)
+
+
+
+-- zynq noc master ports are 32bit, but our slave is 64, so resize
+--local noc_read0_32 = Pulpino.AXIReadBusResize(noc.read,32,64):instantiate("ZynqNOC_NOCSLV_read")
+--local noc_write0_32 = Pulpino.AXIWriteBusResize(noc.write,32,64):instantiate("ZynqNOC_NOC_SLV_write")
+
+local ZynqNOC = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}) -- needs to instantiate pulp noc, but not finalize
+local zynqNOC = ZynqNOC:instantiate("ZynqNOC")
 zynqNOC.extern=true
 
-local noc = Pulpino.AXIInterconnect(3,2):instantiate("pulpinoNOC")
-local regs = SOC.axiRegs( {}, SDF{1,(128*64)/8}, noc.readSource1, noc.readSink1, noc.writeSource1, noc.writeSink1 ):instantiate("regs")
+local noc = Pulpino.AXIInterconnect(2,2,{{zynqNOC.read,zynqNOC.write}}):instantiate("PulpinoNOC")
+
+--noc:addSlaveRead(ZynqNoc.read)
+--noc:addSlaveWrite(ZynqNoc.write)
 
-local IP_plus200 = C.linearPipeline({G.AXIReadBurst{ "frame_128.raw", {128,32}, types.u8, 8, noc.read1, SDF{1,(128*32)/8} },G.HS{G.Map{G.Add{200}}},G.AXIWriteBurst{"out/soc_simple",noc.write1}},"IP_plus100")
+print(ZynqNOC)
+
+local IP_plus200 = C.linearPipeline({G.AXIReadBurst{ "frame_128.raw", {128,32}, types.u8, 8, noc.read, SDF{1,(128*32)/8}, R.Address(0x30008000) },G.MapFramed{G.FIFO{512}},G.HS{G.Map{G.Add{200}}},G.AXIWriteBurst{"out/soc_simple_plus200",noc.write, R.Address(0x3000C000)} },"IP_plus100")
 
 local Inv = G.Module{"Inv",types.u(8),SDF{1,1},function(i) return G.Sub(R.c(255,types.u8),i) end}
 
-local IP_inv = C.linearPipeline({G.AXIReadBurst{ "frame_128.raw", {128,32}, types.u8, 8, noc.read2, SDF{1,(128*32)/8} },G.HS{G.Map{Inv}},G.AXIWriteBurst{"out/soc_simple",noc.write2}},"IP_inv")
+local IP_inv = C.linearPipeline({G.AXIReadBurst{ "frame_128.raw", {128,32}, types.u8, 8, noc.read1, SDF{1,(128*32)/8}, R.Address(0x3000A000) },G.MapFramed{G.FIFO{512}},G.HS{G.Map{G.Add{100}}},G.HS{G.Map{G.Add{100}}},G.AXIWriteBurst{"out/soc_simple_inv",noc.write1, R.Address(0x3000D000)}},"IP_inv")
 
-local PTop = G.Module{"PTop",
+local PTop = G.Module{"PTop",types.HandshakeTrigger,
   function(i)
-    local st = G.FanOut{2}(regs:start(i))
+    local st = G.FanOut{2}(i)
     local done_plus200, done_inv = IP_plus200(st[0]), IP_inv(st[1])
     done_plus200 = G.FIFO{128}(done_plus200)
     done_inv = G.FIFO{128}(done_inv)
 
-    -- zynq noc master ports are 32bit, but our slave is 64, so resize
-    local noc_read0_32 = Pulpino.AXIReadBusResize(noc.read0,32,64)
-    local noc_write0_32 = Pulpino.AXIWriteBusResize(noc.write0,32,64)
 
-    return R.statements{
-      regs:done(G.FanIn(done_plus200,done_inv)),
-      noc:readSink0(zynqNOC:read(noc:readSource0())),
-      noc:writeSink0(zynqNOC:write(noc:writeSource0())),
-      zynqNOC:readSink(noc_read0_32(zynqNOC:readSource())),
-      zynqNOC:writeSink(noc_write0_32(zynqNOC:writeSource()))
-    }
+    --    return regs:done(G.FanIn(done_plus200,done_inv))
+    return G.FanIn(done_plus200,done_inv)
   end}
 
-harness(PTop)
+print(PTop)
+
+print(noc.module)
+
+local Top = C.linearPipeline({regs.start,PTop,regs.done},"Top",nil,{regs,noc})
+
+Top.globalMetadata.InstCall_PulpinoNOC_write1_write_filename=nil
+Top.globalMetadata.InstCall_PulpinoNOC_write_write_filename="out/soc_pulpino_noc"
+Top.globalMetadata.InstCall_PulpinoNOC_write_write_H=64
+
+print(Top)
+--harness({regs.start,PTop,regs.done},nil,{regs,noc})
+harness(Top)

examples/soc_read.lua

@@ -6,9 +6,10 @@ require "types".export()
 local SDF = require "sdf"
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+local regs = SOC.axiRegs({},SDF{1,30*14*9}):instantiate("regs")
+
+local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
 noc.extern=true
-local regs = SOC.axiRegs({},SDF{1,30*14*9},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 PosToAddr = G.Module{ "PosToAddr", ar(u16,2),
   function(loc)