I2S connectivity

I2S connectivity

Wikipedia I2S

The bus consists of at least three lines:

Bit clock line
    Officially "continuous serial clock (SCK)".[1] Typically written "bit clock (BCLK)".[2]
Word clock line
    Officially "word select (WS)".[1] Typically called "left-right clock (LRCLK)"[2] or "frame sync (FS)".[3]
    0 = Left channel, 1 = Right channel[1]
At least one multiplexed data line
    Officially "serial data (SD)",[1] but can be called SDATA, SDIN, SDOUT, DACDAT, ADCDAT, etc.[2]

It may also include the following lines:

Master clock (typically 256 x LRCLK)
    This is not part of the I2S standard,[4] but is commonly included for synchronizing the internal operation of the analog/digital converters.[3][5]
A multiplexed data line for upload