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  1. prjxray-db prjxray-db Public

    Forked from f4pga/prjxray-db

    Project X-Ray Database: XC7 Series

    Shell 3 1

  2. openstellina openstellina Public

    Stellina status display

    Standard ML 3

  3. greth_library greth_library Public

    A debugging transport based on greth 10/100Mbit and riscv_vhdl

    Verilog 2 2

  4. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

    SystemVerilog 2 1

  5. sysver2ver sysver2ver Public

    Forked from jrrk/sysver2ver

    Converting System Verilog to plain Verilog using .xml dump from Verilator

    Verilog 2

  6. riscv_jtag_server riscv_jtag_server Public

    C 1 5