Question about naked attribute

[ryanpatiency]

mini-arm-os/08-CMSIS/core/src/threads.c

Line 19 in f88e0be

/* Caution: Without naked attribute, GCC will normally push r7 which is used

In the comment linked by, it indicate r7 is for sp, but sp is r13 instead. Also quoting from Arm-Cortex-M3 technical reference:

"After returning from the ISR, the processor automatically pops the eight registers from the stack. Interrupt return is passed as a data field in the LR, so ISR functions can be normal C/C++ functions, and do not require a veneer."

So I wonder if we need naked attribute at all

[jserv]

@lecopzer, can you clarify?

[lecopzer]

HI @ryanpatiency

In the comment linked by, it indicate r7 is for sp, but sp is r13 instead. Also quoting from Arm-Cortex-M3 technical reference:

Sorry I don't get the point, "store sp in r7" and "sp is r13" do not conflict with each other.

"After returning from the ISR, the processor automatically pops the eight registers from the stack. Interrupt return is passed as a data field in the LR, so ISR functions can be normal C/C++ functions, and do not require a veneer."

This talks about how exception return works.
Since PendSV is not a _normal_ ISR, it deals with context switch and never return, we have to handle calling convention ourselves and avoid GCC store any thing at function prologue; otherwise GCC would corrupt our context switch implementation.

So I wonder if we need naked attribute at all

Could you please disassemble for both function with and without naked attribute, and explicitly point out anything you thought it's unreasonable?

If you have any question, feel free to ask.
Thanks

[ryanpatiency]

Hi @lecopzer,
Thanks for your illustration, the concept is clear after I compared the disassembled pendsv function, the function without naked attribute modify the r7 without restoring it, thus might affect the user program.

Thank you

[jserv]

Answered.