CR0.TS flag is unreliable

[jwt27]

The fpu context switching routines previously relied on the TS flag in CR0 to trigger exception 07. What I found is that, in many cases, the TS flag is already cleared upon entering this exception. I'm now using the EM flag to achieve the same effect.

Using TS is the 'nice' way to do it, since that is its intended purpose, so I would prefer to use that if possible. I'm guessing the DPMI host or some real-mode code clears this flag at some point, however I briefly inspected the HDPMI sources and was unable to find any such code.

[jwt27]

Stale issue, CR0.EM works fine for this purpose.