You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
This is not correct, mainly because how each stage is driven by the clocks sent from the pipeline. When I created the register bank, I used the negative edge because I had in mind the clock scheme of a processor with no pipeline.
The text was updated successfully, but these errors were encountered:
This is not correct, mainly because how each stage is driven by the clocks sent from the pipeline. When I created the register bank, I used the negative edge because I had in mind the clock scheme of a processor with no pipeline.
The text was updated successfully, but these errors were encountered: