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Implementation - Register Bank #7

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Kammann123 opened this issue May 16, 2021 · 1 comment

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Kammann123 commented May 16, 2021

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Kammann123 commented May 17, 2021

I've been thinking of this and it wouldn't be so hard to implement...

Create an input/output enabled register using the Register, AND gate and Buffer tristate
Create the A, B, and C decoders
Wire the Register Bank

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