limit fb divider so max pll frequency is ~150M.

[mattvenn]

Tim Edwards says:

Specifically, line 60 shows that the DCO does not quite make it to 150MHz, topping out at around 143 on the chip I was testing. That means if you try to get it to 150, it won't make it, and it won't lock. But you should still see a clock running, unlocked, at the maximum rate divided by 5.

https://docs.google.com/spreadsheets/d/1aSsOAUdh271JG_9bOfwnNPPrp_jr7t5lCL5PqHTinYs/edit#gid=340090133