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  • Xilinx
  • San José, California

Organizations

@Xilinx @Par4All @triSYCL

Pinned repositories

  1. triSYCL

    Forked from triSYCL/triSYCL

    An open source implementation of OpenCL SYCL from Khronos Group

    C 1

  2. Par4All/par4all

    Par4All is an automatic parallelizing and optimizing compiler (workbench) for C and Fortran sequential programs

    C 28 8

  3. BitWizard_SPI_relay

    A modern C++ interface to control the Raspberry SPI Relay card from BitWizard for Raspberry Pi

    C++

  4. smecc

    The smecc compiler of the SME-C #pragma-based language developed in the European SMECY project

    C

325 contributions in the last year

Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Mon Wed Fri

Contribution activity

August 2018

Created a pull request in KhronosGroup/SyclParallelSTL that received 2 comments

Update benchmarks with new member function names from nd_item to match SYCL 1.2.1 rev 3

That is strange, it looks like Travis-CI does not check the compilation of the benchmarks, otherwise this would have been detected... If you agree …

+4 −4 2 comments

Created an issue in ORNL/cpp-proposals-pub that received 16 comments

Traditional access a[i][j]k] seems missing

It looks like the current proposal does not have the usual a[j][j][k] syntax. Since it cannot be an omission :-) , what are the reasons for this ab…

16 comments
2 contributions in private repositories Aug 19

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