{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":45276958,"defaultBranch":"master","name":"gcc","ownerLogin":"kraj","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2015-10-30T21:16:25.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/465279?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1719602009.0","currentOid":""},"activityList":{"items":[{"before":"11049cdf204bc96bc407e5dd44ed3b8a492f405a","after":"f8c130cdf531653e5c041d247729851419bc7bde","ref":"refs/heads/trunk","pushedAt":"2024-07-04T19:14:40.000Z","pushType":"push","commitsCount":7,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"analyzer: convert sm_context * to sm_context &\n\nThese are never nullptr and never change, so use a reference rather\nthan a pointer.\n\nNo functional change intended.\n\ngcc/analyzer/ChangeLog:\n\t* diagnostic-manager.cc\n\t(diagnostic_manager::add_events_for_eedge): Pass sm_ctxt by\n\treference.\n\t* engine.cc (impl_region_model_context::on_condition): Likewise.\n\t(impl_region_model_context::on_bounded_ranges): Likewise.\n\t(impl_region_model_context::on_phi): Likewise.\n\t(exploded_node::on_stmt): Likewise.\n\t* sm-fd.cc: Update all uses of sm_context * to sm_context &.\n\t* sm-file.cc: Likewise.\n\t* sm-malloc.cc: Likewise.\n\t* sm-pattern-test.cc: Likewise.\n\t* sm-sensitive.cc: Likewise.\n\t* sm-signal.cc: Likewise.\n\t* sm-taint.cc: Likewise.\n\t* sm.h: Likewise.\n\t* varargs.cc: Likewise.\n\ngcc/testsuite/ChangeLog:\n\t* gcc.dg/plugin/analyzer_gil_plugin.c: Update all uses of\n\tsm_context * to sm_context &.\n\nSigned-off-by: David Malcolm ","shortMessageHtmlLink":"analyzer: convert sm_context * to sm_context &"}},{"before":"0f71e52717b20c41c168b57245a8c12bdaa017e3","after":"dc63b5dbe60da076f46cb3bcb10f0f84cfd7fb7d","ref":"refs/heads/releases/gcc-14","pushedAt":"2024-07-04T19:14:09.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro\n\nThe ACLE requires __ARM_FEATURE_SVE_BF16 to be enabled when SVE and BF16\nand the associated intrinsics are available.\nGCC does support the required intrinsics for TARGET_SVE_BF16 so define\nthis macro too.\n\nBootstrapped and tested on aarch64-none-linux-gnu.\n\ngcc/\n\n\tPR target/115475\n\t* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):\n\tDefine __ARM_FEATURE_SVE_BF16 for TARGET_SVE_BF16.\n\ngcc/testsuite/\n\n\tPR target/115475\n\t* gcc.target/aarch64/acle/bf16_sve_feature.c: New test.\n\nSigned-off-by: Kyrylo Tkachov \n(cherry picked from commit 6492c7130d6ae9992298fc3d072e2589d1131376)","shortMessageHtmlLink":"aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro"}},{"before":"a26c560d3f679d5237dd5191869e845740b94759","after":"40d54856c1189ab6125d3eeb064df25082dd0e50","ref":"refs/heads/releases/gcc-13","pushedAt":"2024-07-04T19:14:08.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro\n\nThe ACLE requires __ARM_FEATURE_SVE_BF16 to be enabled when SVE and BF16\nand the associated intrinsics are available.\nGCC does support the required intrinsics for TARGET_SVE_BF16 so define\nthis macro too.\n\nBootstrapped and tested on aarch64-none-linux-gnu.\n\ngcc/\n\n\tPR target/115475\n\t* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):\n\tDefine __ARM_FEATURE_SVE_BF16 for TARGET_SVE_BF16.\n\ngcc/testsuite/\n\n\tPR target/115475\n\t* gcc.target/aarch64/acle/bf16_sve_feature.c: New test.\n\nSigned-off-by: Kyrylo Tkachov \n(cherry picked from commit 6492c7130d6ae9992298fc3d072e2589d1131376)","shortMessageHtmlLink":"aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro"}},{"before":"843eba6f38d3debc44fe4ec4084aaaf9d5907485","after":"cdeb7ce83f71d1527626975e70d294ef55535d03","ref":"refs/heads/releases/gcc-12","pushedAt":"2024-07-04T19:14:06.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro\n\nThe ACLE requires __ARM_FEATURE_SVE_BF16 to be enabled when SVE and BF16\nand the associated intrinsics are available.\nGCC does support the required intrinsics for TARGET_SVE_BF16 so define\nthis macro too.\n\nBootstrapped and tested on aarch64-none-linux-gnu.\n\ngcc/\n\n\tPR target/115475\n\t* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):\n\tDefine __ARM_FEATURE_SVE_BF16 for TARGET_SVE_BF16.\n\ngcc/testsuite/\n\n\tPR target/115475\n\t* gcc.target/aarch64/acle/bf16_sve_feature.c: New test.\n\nSigned-off-by: Kyrylo Tkachov \n(cherry picked from commit 6492c7130d6ae9992298fc3d072e2589d1131376)","shortMessageHtmlLink":"aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro"}},{"before":"11049cdf204bc96bc407e5dd44ed3b8a492f405a","after":"f8c130cdf531653e5c041d247729851419bc7bde","ref":"refs/heads/master","pushedAt":"2024-07-04T19:13:59.000Z","pushType":"push","commitsCount":7,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"analyzer: convert sm_context * to sm_context &\n\nThese are never nullptr and never change, so use a reference rather\nthan a pointer.\n\nNo functional change intended.\n\ngcc/analyzer/ChangeLog:\n\t* diagnostic-manager.cc\n\t(diagnostic_manager::add_events_for_eedge): Pass sm_ctxt by\n\treference.\n\t* engine.cc (impl_region_model_context::on_condition): Likewise.\n\t(impl_region_model_context::on_bounded_ranges): Likewise.\n\t(impl_region_model_context::on_phi): Likewise.\n\t(exploded_node::on_stmt): Likewise.\n\t* sm-fd.cc: Update all uses of sm_context * to sm_context &.\n\t* sm-file.cc: Likewise.\n\t* sm-malloc.cc: Likewise.\n\t* sm-pattern-test.cc: Likewise.\n\t* sm-sensitive.cc: Likewise.\n\t* sm-signal.cc: Likewise.\n\t* sm-taint.cc: Likewise.\n\t* sm.h: Likewise.\n\t* varargs.cc: Likewise.\n\ngcc/testsuite/ChangeLog:\n\t* gcc.dg/plugin/analyzer_gil_plugin.c: Update all uses of\n\tsm_context * to sm_context &.\n\nSigned-off-by: David Malcolm ","shortMessageHtmlLink":"analyzer: convert sm_context * to sm_context &"}},{"before":"e40d881845431f7aa9c1ea1efd787cada3a53fb0","after":"63fd275d3ce19c7f85497d4753e45221088c320c","ref":"refs/heads/oe/master","pushedAt":"2024-07-04T15:53:25.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Append GCC private include paths on musl instead of prepending\n\nMusl does not need gcc private compiler headers, therefore use them\nafter standard system header search paths.\n\nThis fixes packages like python builds to detect the musl systems\ncorreclty, as it looks for musl specific stuff in stdarg.h system\nheader, which is wrongly picked from gcc private headers in OE\n\nUpstream-Status: Submitted [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115368]\nSigned-off-by: Khem Raj ","shortMessageHtmlLink":"Append GCC private include paths on musl instead of prepending"}},{"before":"2b1d4279d9d835ff44dc5b252ce03a899d32c1fa","after":"7dfac0c9aa20c5f815b94b32878cd48fcbf9d00b","ref":"refs/heads/oe/gcc-14","pushedAt":"2024-07-04T15:53:10.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie \nSigned-off-by: Khem Raj ","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"622fcc67d735e0ed8c6bc84aba7cbab4cb6af898","after":"55d60971b30a5110b428deb8df3fa7b82b9a65c2","ref":"refs/heads/oe/gcc-13","pushedAt":"2024-07-04T15:52:52.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie \nSigned-off-by: Khem Raj ","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"e5f73853ae78d4e9ae434c707a12da1494459b24","after":"11049cdf204bc96bc407e5dd44ed3b8a492f405a","ref":"refs/heads/trunk","pushedAt":"2024-07-04T07:23:54.000Z","pushType":"push","commitsCount":11,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Aarch64, bugfix: Fix NEON bigendian addp intrinsic [PR114890]\n\nThis change removes code that switches the operands in bigendian mode erroneously.\nThis fixes the related test also.\n\ngcc/ChangeLog:\n\n\tPR target/114890\n\t* config/aarch64/aarch64-simd.md: Remove bigendian operand swap.\n\ngcc/testsuite/ChangeLog:\n\n\tPR target/114890\n\t* gcc.target/aarch64/vector_intrinsics_asm.c: Remove xfail.","shortMessageHtmlLink":"Aarch64, bugfix: Fix NEON bigendian addp intrinsic [PR114890]"}},{"before":"6e1fb1f9db3b722598a7332b92f4470a7bbc9c95","after":"0f71e52717b20c41c168b57245a8c12bdaa017e3","ref":"refs/heads/releases/gcc-14","pushedAt":"2024-07-04T07:23:22.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"ecd6ebe5fb0151f9649705a5798325032bbc811a","after":"a26c560d3f679d5237dd5191869e845740b94759","ref":"refs/heads/releases/gcc-13","pushedAt":"2024-07-04T07:23:20.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"0c98d9479cec88148eb3be8d0098e36bce061cd6","after":"843eba6f38d3debc44fe4ec4084aaaf9d5907485","ref":"refs/heads/releases/gcc-12","pushedAt":"2024-07-04T07:23:18.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"ce713016fb50796e906e39ba4244fbaf47ae77a9","after":"5f2b94f9b342702a3027a22fc7abe421ad91c28f","ref":"refs/heads/releases/gcc-11","pushedAt":"2024-07-04T07:23:17.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"e5f73853ae78d4e9ae434c707a12da1494459b24","after":"11049cdf204bc96bc407e5dd44ed3b8a492f405a","ref":"refs/heads/master","pushedAt":"2024-07-04T07:23:11.000Z","pushType":"push","commitsCount":11,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Aarch64, bugfix: Fix NEON bigendian addp intrinsic [PR114890]\n\nThis change removes code that switches the operands in bigendian mode erroneously.\nThis fixes the related test also.\n\ngcc/ChangeLog:\n\n\tPR target/114890\n\t* config/aarch64/aarch64-simd.md: Remove bigendian operand swap.\n\ngcc/testsuite/ChangeLog:\n\n\tPR target/114890\n\t* gcc.target/aarch64/vector_intrinsics_asm.c: Remove xfail.","shortMessageHtmlLink":"Aarch64, bugfix: Fix NEON bigendian addp intrinsic [PR114890]"}},{"before":"a5618269852ccf878370d43978d01026e9fd786d","after":"e40d881845431f7aa9c1ea1efd787cada3a53fb0","ref":"refs/heads/oe/master","pushedAt":"2024-07-04T03:29:15.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Append GCC private include paths on musl instead of prepending\n\nMusl does not need gcc private compiler headers, therefore use them\nafter standard system header search paths.\n\nThis fixes packages like python builds to detect the musl systems\ncorreclty, as it looks for musl specific stuff in stdarg.h system\nheader, which is wrongly picked from gcc private headers in OE\n\nUpstream-Status: Submitted [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115368]\nSigned-off-by: Khem Raj ","shortMessageHtmlLink":"Append GCC private include paths on musl instead of prepending"}},{"before":"bdd585e649a22b54140166edda370a496701e21a","after":"2b1d4279d9d835ff44dc5b252ce03a899d32c1fa","ref":"refs/heads/oe/gcc-14","pushedAt":"2024-07-04T03:29:01.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie \nSigned-off-by: Khem Raj ","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"9036a028e961f70d01df38e9dfcd651ca8ceb4af","after":"622fcc67d735e0ed8c6bc84aba7cbab4cb6af898","ref":"refs/heads/oe/gcc-13","pushedAt":"2024-07-04T03:28:45.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie \nSigned-off-by: Khem Raj ","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"038d64f62271ddc62aa35d0a5dfd3843fdb9e6d7","after":"e5f73853ae78d4e9ae434c707a12da1494459b24","ref":"refs/heads/trunk","pushedAt":"2024-07-03T19:14:31.000Z","pushType":"push","commitsCount":25,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"[committed] Fix previously latent bug in reorg affecting cris port\n\nThe late-combine patch has triggered a previously latent bug in reorg.\n\nBasically we have a sequence like this in the middle of reorg before we start\nrelaxing delay slots (cris-elf, gcc.dg/torture/pr98289.c)\n\n> (insn 67 49 18 (sequence [\n> (jump_insn 50 49 52 (set (pc)\n> (if_then_else (ne (reg:CC 19 ccr)\n> (const_int 0 [0]))\n> (label_ref:SI 30)\n> (pc))) \"j.c\":10:6 discrim 1 282 {*bnecc}\n> (expr_list:REG_DEAD (reg:CC 19 ccr)\n> (int_list:REG_BR_PROB 7 (nil)))\n> -> 30)\n> (insn/f 52 50 18 (set (mem:SI (reg/f:SI 14 sp) [1 S4 A8])\n> (reg:SI 16 srp)) 37 {*mov_tomemsi}\n> (nil))\n> ]) \"j.c\":10:6 discrim 1 -1\n> (nil))\n>\n> (note 18 67 54 [bb 3] NOTE_INSN_BASIC_BLOCK)\n>\n> (note 54 18 55 NOTE_INSN_EPILOGUE_BEG)\n>\n> (jump_insn 55 54 56 (return) \"j.c\":14:1 228 {*return_expanded}\n> (nil)\n> -> return)\n>\n> (barrier 56 55 43)\n>\n> (note 43 56 65 [bb 4] NOTE_INSN_BASIC_BLOCK)\n>\n> (note 65 43 30 NOTE_INSN_SWITCH_TEXT_SECTIONS)\n>\n> (code_label 30 65 8 5 6 (nil) [1 uses])\n>\n> (note 8 30 61 [bb 5] NOTE_INSN_BASIC_BLOCK)\n\nSo at a high level the things to note are that insn 50 conditionally jumps\naround insn 55. Second there's a SWITCH_TEXT_SECTIONS note between insn 50 and\nthe target label for insn 50 (code_label 30).\n\nreorg sees the conditional jump around the unconditional jump/return and will\ninvert the jump and retarget the original jump to an appropriate location. In\nthis case generating:\n\n> (insn 67 49 18 (sequence [\n> (jump_insn 50 49 52 (set (pc)\n> (if_then_else (eq (reg:CC 19 ccr)\n> (const_int 0 [0]))\n> (label_ref:SI 68)\n> (pc))) \"j.c\":10:6 discrim 1 281 {*beqcc}\n> (expr_list:REG_DEAD (reg:CC 19 ccr)\n> (int_list:REG_BR_PROB 1073741831 (nil)))\n> -> 68)\n> (insn/s/f 52 50 18 (set (mem:SI (reg/f:SI 14 sp) [1 S4 A8])\n> (reg:SI 16 srp)) 37 {*mov_tomemsi}\n> (nil))\n> ]) \"j.c\":10:6 discrim 1 -1\n> (nil))\n>\n> (note 18 67 54 [bb 3] NOTE_INSN_BASIC_BLOCK)\n>\n> (note 54 18 43 NOTE_INSN_EPILOGUE_BEG)\n>\n> (note 43 54 65 [bb 4] NOTE_INSN_BASIC_BLOCK)\n>\n> (note 65 43 8 NOTE_INSN_SWITCH_TEXT_SECTIONS)\n>\n> (note 8 65 61 [bb 5] NOTE_INSN_BASIC_BLOCK)\n[ ... ]\nWhere the new target of the jump is a return statement later in the IL.\n\nNote that we now have a SWITCH_TEXT_SECTIONS note that is not immediately\npreceded by a BARRIER. That triggers an assertion in the dwarf2 code. Removal\nof the BARRIER is inherent in this optimization.\n\nThe fix is simple, we avoid this optimization when there's a\nSWITCH_TEXT_SECTIONS note between the conditional jump insn and its target.\nThankfully we already have a routine to test for this in reorg, so we just need\nto call it appropriately. The other approach would be to drop the note which I\nconsidered and discarded.\n\nWe don't have great coverage for delay slot targets. I've tested arc, cris,\nfr30, frv, h8, iq2000, microblaze, or1k, sh3 visium in my tester as crosses\nwithout new regressions, fixing one regression along the way. Bootstrap &\nregression testing on sh4 and hppa will take considerably longer.\n\ngcc/\n\n\t* reorg.cc (relax_delay_slots): Do not optimize a conditional\n\tjump around an unconditional jump/return in the presence of\n\ta text section switch.","shortMessageHtmlLink":"[committed] Fix previously latent bug in reorg affecting cris port"}},{"before":"052f78d010d224c7289f1cf6eec784ac4eeed351","after":"6e1fb1f9db3b722598a7332b92f4470a7bbc9c95","ref":"refs/heads/releases/gcc-14","pushedAt":"2024-07-03T19:14:01.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Revert \"Delete MALLOC_ABI_ALIGNMENT define from pa32-linux.h\"\n\nThis reverts commit 0ee3266b3dec4d984d43c79e2b3e649256e3eaaa.","shortMessageHtmlLink":"Revert \"Delete MALLOC_ABI_ALIGNMENT define from pa32-linux.h\""}},{"before":"bab38d9271ce3f26cb64b8cb712351eb3fedd559","after":"ecd6ebe5fb0151f9649705a5798325032bbc811a","ref":"refs/heads/releases/gcc-13","pushedAt":"2024-07-03T19:13:59.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu patterns\n\n2024-06-30 John David Anglin \n\ngcc/ChangeLog:\n\n\tPR target/115691\n\t* config/pa/pa.md: Remove incorrect xmpyu patterns.","shortMessageHtmlLink":"hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu …"}},{"before":"ca6eea0eb33de8b2e23e0bef3466575bb14ab63f","after":"0c98d9479cec88148eb3be8d0098e36bce061cd6","ref":"refs/heads/releases/gcc-12","pushedAt":"2024-07-03T19:13:57.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu patterns\n\n2024-06-30 John David Anglin \n\ngcc/ChangeLog:\n\n\tPR target/115691\n\t* config/pa/pa.md: Remove incorrect xmpyu patterns.","shortMessageHtmlLink":"hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu …"}},{"before":"2c8c0b3b972796158be365922c80ec624602ea44","after":"ce713016fb50796e906e39ba4244fbaf47ae77a9","ref":"refs/heads/releases/gcc-11","pushedAt":"2024-07-03T19:13:55.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu patterns\n\n2024-06-30 John David Anglin \n\ngcc/ChangeLog:\n\n\tPR target/115691\n\t* config/pa/pa.md: Remove incorrect xmpyu patterns.","shortMessageHtmlLink":"hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu …"}},{"before":"038d64f62271ddc62aa35d0a5dfd3843fdb9e6d7","after":"e5f73853ae78d4e9ae434c707a12da1494459b24","ref":"refs/heads/master","pushedAt":"2024-07-03T19:13:49.000Z","pushType":"push","commitsCount":25,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"[committed] Fix previously latent bug in reorg affecting cris port\n\nThe late-combine patch has triggered a previously latent bug in reorg.\n\nBasically we have a sequence like this in the middle of reorg before we start\nrelaxing delay slots (cris-elf, gcc.dg/torture/pr98289.c)\n\n> (insn 67 49 18 (sequence [\n> (jump_insn 50 49 52 (set (pc)\n> (if_then_else (ne (reg:CC 19 ccr)\n> (const_int 0 [0]))\n> (label_ref:SI 30)\n> (pc))) \"j.c\":10:6 discrim 1 282 {*bnecc}\n> (expr_list:REG_DEAD (reg:CC 19 ccr)\n> (int_list:REG_BR_PROB 7 (nil)))\n> -> 30)\n> (insn/f 52 50 18 (set (mem:SI (reg/f:SI 14 sp) [1 S4 A8])\n> (reg:SI 16 srp)) 37 {*mov_tomemsi}\n> (nil))\n> ]) \"j.c\":10:6 discrim 1 -1\n> (nil))\n>\n> (note 18 67 54 [bb 3] NOTE_INSN_BASIC_BLOCK)\n>\n> (note 54 18 55 NOTE_INSN_EPILOGUE_BEG)\n>\n> (jump_insn 55 54 56 (return) \"j.c\":14:1 228 {*return_expanded}\n> (nil)\n> -> return)\n>\n> (barrier 56 55 43)\n>\n> (note 43 56 65 [bb 4] NOTE_INSN_BASIC_BLOCK)\n>\n> (note 65 43 30 NOTE_INSN_SWITCH_TEXT_SECTIONS)\n>\n> (code_label 30 65 8 5 6 (nil) [1 uses])\n>\n> (note 8 30 61 [bb 5] NOTE_INSN_BASIC_BLOCK)\n\nSo at a high level the things to note are that insn 50 conditionally jumps\naround insn 55. Second there's a SWITCH_TEXT_SECTIONS note between insn 50 and\nthe target label for insn 50 (code_label 30).\n\nreorg sees the conditional jump around the unconditional jump/return and will\ninvert the jump and retarget the original jump to an appropriate location. In\nthis case generating:\n\n> (insn 67 49 18 (sequence [\n> (jump_insn 50 49 52 (set (pc)\n> (if_then_else (eq (reg:CC 19 ccr)\n> (const_int 0 [0]))\n> (label_ref:SI 68)\n> (pc))) \"j.c\":10:6 discrim 1 281 {*beqcc}\n> (expr_list:REG_DEAD (reg:CC 19 ccr)\n> (int_list:REG_BR_PROB 1073741831 (nil)))\n> -> 68)\n> (insn/s/f 52 50 18 (set (mem:SI (reg/f:SI 14 sp) [1 S4 A8])\n> (reg:SI 16 srp)) 37 {*mov_tomemsi}\n> (nil))\n> ]) \"j.c\":10:6 discrim 1 -1\n> (nil))\n>\n> (note 18 67 54 [bb 3] NOTE_INSN_BASIC_BLOCK)\n>\n> (note 54 18 43 NOTE_INSN_EPILOGUE_BEG)\n>\n> (note 43 54 65 [bb 4] NOTE_INSN_BASIC_BLOCK)\n>\n> (note 65 43 8 NOTE_INSN_SWITCH_TEXT_SECTIONS)\n>\n> (note 8 65 61 [bb 5] NOTE_INSN_BASIC_BLOCK)\n[ ... ]\nWhere the new target of the jump is a return statement later in the IL.\n\nNote that we now have a SWITCH_TEXT_SECTIONS note that is not immediately\npreceded by a BARRIER. That triggers an assertion in the dwarf2 code. Removal\nof the BARRIER is inherent in this optimization.\n\nThe fix is simple, we avoid this optimization when there's a\nSWITCH_TEXT_SECTIONS note between the conditional jump insn and its target.\nThankfully we already have a routine to test for this in reorg, so we just need\nto call it appropriately. The other approach would be to drop the note which I\nconsidered and discarded.\n\nWe don't have great coverage for delay slot targets. I've tested arc, cris,\nfr30, frv, h8, iq2000, microblaze, or1k, sh3 visium in my tester as crosses\nwithout new regressions, fixing one regression along the way. Bootstrap &\nregression testing on sh4 and hppa will take considerably longer.\n\ngcc/\n\n\t* reorg.cc (relax_delay_slots): Do not optimize a conditional\n\tjump around an unconditional jump/return in the presence of\n\ta text section switch.","shortMessageHtmlLink":"[committed] Fix previously latent bug in reorg affecting cris port"}},{"before":"cc63b59e8843f049587b7a548a530f710085e577","after":"038d64f62271ddc62aa35d0a5dfd3843fdb9e6d7","ref":"refs/heads/trunk","pushedAt":"2024-07-03T07:14:14.000Z","pushType":"push","commitsCount":11,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"preprocessor: Create the parser before handling command-line includes [PR115312]\n\nSince r14-2893, we create a parser object in preprocess-only mode for the\npurpose of parsing #pragma while preprocessing. The parser object was\nformerly created after calling c_finish_options(), which leads to problems\non platforms that don't use stdc-predef.h (such as MinGW, as reported in\nthe PR). On such platforms, the call to c_finish_options() will process\nthe first command-line-specified include file. If that includes a PCH, then\nc-ppoutput.cc will encounter a state it did not anticipate. Fix it by\ncreating the parser prior to calling c_finish_options().\n\ngcc/c-family/ChangeLog:\n\n\tPR pch/115312\n\t* c-opts.cc (c_common_init): Call c_init_preprocess() before\n\tc_finish_options() so that a parser is available to process any\n\tincludes specified on the command line.\n\ngcc/testsuite/ChangeLog:\n\n\tPR pch/115312\n\t* g++.dg/pch/pr115312.C: New test.\n\t* g++.dg/pch/pr115312.Hs: New test.","shortMessageHtmlLink":"preprocessor: Create the parser before handling command-line includes…"}},{"before":"8eb469546f7f32dcec5d3376dfb419c1d4f21e4a","after":"052f78d010d224c7289f1cf6eec784ac4eeed351","ref":"refs/heads/releases/gcc-14","pushedAt":"2024-07-03T07:13:43.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"rs6000: Fix wrong RTL patterns for vector merge high/low short on LE\n\nCommit r12-4496 changes some define_expands and define_insns\nfor vector merge high/low short, which are altivec_vmrg[hl]h.\nThese defines are mainly for built-in function vec_merge{h,l}\nand some internal gen function needs. These functions should\nconsider endianness, taking vec_mergeh as example, as PVIPR\ndefines, vec_mergeh \"Merges the first halves (in element order)\nof two vectors\", it does note it's in element order. So it's\nmapped into vmrghh on BE while vmrglh on LE respectively.\nAlthough the mapped insns are different, as the discussion in\nPR106069, the RTL pattern should be still the same, it is\nconformed before commit r12-4496, but gets changed into\ndifferent patterns on BE and LE starting from commit r12-4496.\nSimilar to 32-bit element case in commit log of r15-1504, this\n16-bit element pattern on LE doesn't actually match what the\nunderlying insn is intended to represent, once some optimization\nlike combine does some changes basing on it, it would cause\nthe unexpected consequence. The newly constructed test case\npr106069-2.c is a typical example for this issue on element type\nshort.\n\nSo this patch is to fix the wrong RTL pattern, ensure the\nassociated RTL patterns become the same as before which can\nhave the same semantic as their mapped insns. With the\nproposed patch, the expanders like altivec_vmrghh expands\ninto altivec_vmrghh_direct_be or altivec_vmrglh_direct_le\ndepending on endianness, \"direct\" can easily show which\ninsn would be generated, _be and _le are mainly for the\ndifferent RTL patterns as endianness.\n\nCo-authored-by: Xionghu Luo \n\n\tPR target/106069\n\tPR target/115355\n\ngcc/ChangeLog:\n\n\t* config/rs6000/altivec.md (altivec_vmrghh_direct): Rename to ...\n\t(altivec_vmrghh_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.\n\t(altivec_vmrghh_direct_le): New define_insn.\n\t(altivec_vmrglh_direct): Rename to ...\n\t(altivec_vmrglh_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.\n\t(altivec_vmrglh_direct_le): New define_insn.\n\t(altivec_vmrghh): Adjust by calling gen_altivec_vmrghh_direct_be\n\tfor BE and gen_altivec_vmrglh_direct_le for LE.\n\t(altivec_vmrglh): Adjust by calling gen_altivec_vmrglh_direct_be\n\tfor BE and gen_altivec_vmrghh_direct_le for LE.\n\t(vec_widen_umult_hi_v16qi): Adjust the call to\n\tgen_altivec_vmrghh_direct by gen_altivec_vmrghh for BE\n\tand by gen_altivec_vmrglh for LE.\n\t(vec_widen_smult_hi_v16qi): Likewise.\n\t(vec_widen_umult_lo_v16qi): Adjust the call to\n\tgen_altivec_vmrglh_direct by gen_altivec_vmrglh for BE\n\tand by gen_altivec_vmrghh for LE.\n\t(vec_widen_smult_lo_v16qi): Likewise.\n\t* config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace\n\tCODE_FOR_altivec_vmrghh_direct by\n\tCODE_FOR_altivec_vmrghh_direct_be for BE and\n\tCODE_FOR_altivec_vmrghh_direct_le for LE. And replace\n\tCODE_FOR_altivec_vmrglh_direct by\n\tCODE_FOR_altivec_vmrglh_direct_be for BE and\n\tCODE_FOR_altivec_vmrglh_direct_le for LE.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/powerpc/pr106069-2.c: New test.\n\n(cherry picked from commit 812c70bf4981958488331d4ea5af8709b5321da1)","shortMessageHtmlLink":"rs6000: Fix wrong RTL patterns for vector merge high/low short on LE"}},{"before":"b4abe8f7f5c3269d058b176fa00fe5c71de05c68","after":"bab38d9271ce3f26cb64b8cb712351eb3fedd559","ref":"refs/heads/releases/gcc-13","pushedAt":"2024-07-03T07:13:42.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"rs6000: Fix wrong RTL patterns for vector merge high/low short on LE\n\nCommit r12-4496 changes some define_expands and define_insns\nfor vector merge high/low short, which are altivec_vmrg[hl]h.\nThese defines are mainly for built-in function vec_merge{h,l}\nand some internal gen function needs. These functions should\nconsider endianness, taking vec_mergeh as example, as PVIPR\ndefines, vec_mergeh \"Merges the first halves (in element order)\nof two vectors\", it does note it's in element order. So it's\nmapped into vmrghh on BE while vmrglh on LE respectively.\nAlthough the mapped insns are different, as the discussion in\nPR106069, the RTL pattern should be still the same, it is\nconformed before commit r12-4496, but gets changed into\ndifferent patterns on BE and LE starting from commit r12-4496.\nSimilar to 32-bit element case in commit log of r15-1504, this\n16-bit element pattern on LE doesn't actually match what the\nunderlying insn is intended to represent, once some optimization\nlike combine does some changes basing on it, it would cause\nthe unexpected consequence. The newly constructed test case\npr106069-2.c is a typical example for this issue on element type\nshort.\n\nSo this patch is to fix the wrong RTL pattern, ensure the\nassociated RTL patterns become the same as before which can\nhave the same semantic as their mapped insns. With the\nproposed patch, the expanders like altivec_vmrghh expands\ninto altivec_vmrghh_direct_be or altivec_vmrglh_direct_le\ndepending on endianness, \"direct\" can easily show which\ninsn would be generated, _be and _le are mainly for the\ndifferent RTL patterns as endianness.\n\nCo-authored-by: Xionghu Luo \n\n\tPR target/106069\n\tPR target/115355\n\ngcc/ChangeLog:\n\n\t* config/rs6000/altivec.md (altivec_vmrghh_direct): Rename to ...\n\t(altivec_vmrghh_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.\n\t(altivec_vmrghh_direct_le): New define_insn.\n\t(altivec_vmrglh_direct): Rename to ...\n\t(altivec_vmrglh_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.\n\t(altivec_vmrglh_direct_le): New define_insn.\n\t(altivec_vmrghh): Adjust by calling gen_altivec_vmrghh_direct_be\n\tfor BE and gen_altivec_vmrglh_direct_le for LE.\n\t(altivec_vmrglh): Adjust by calling gen_altivec_vmrglh_direct_be\n\tfor BE and gen_altivec_vmrghh_direct_le for LE.\n\t(vec_widen_umult_hi_v16qi): Adjust the call to\n\tgen_altivec_vmrghh_direct by gen_altivec_vmrghh for BE\n\tand by gen_altivec_vmrglh for LE.\n\t(vec_widen_smult_hi_v16qi): Likewise.\n\t(vec_widen_umult_lo_v16qi): Adjust the call to\n\tgen_altivec_vmrglh_direct by gen_altivec_vmrglh for BE\n\tand by gen_altivec_vmrghh for LE.\n\t(vec_widen_smult_lo_v16qi): Likewise.\n\t* config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace\n\tCODE_FOR_altivec_vmrghh_direct by\n\tCODE_FOR_altivec_vmrghh_direct_be for BE and\n\tCODE_FOR_altivec_vmrghh_direct_le for LE. And replace\n\tCODE_FOR_altivec_vmrglh_direct by\n\tCODE_FOR_altivec_vmrglh_direct_be for BE and\n\tCODE_FOR_altivec_vmrglh_direct_le for LE.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/powerpc/pr106069-2.c: New test.\n\n(cherry picked from commit 812c70bf4981958488331d4ea5af8709b5321da1)","shortMessageHtmlLink":"rs6000: Fix wrong RTL patterns for vector merge high/low short on LE"}},{"before":"4351caffa7f9112712ce396421d95f7bad90a8f3","after":"ca6eea0eb33de8b2e23e0bef3466575bb14ab63f","ref":"refs/heads/releases/gcc-12","pushedAt":"2024-07-03T07:13:40.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"rs6000: Fix wrong RTL patterns for vector merge high/low short on LE\n\nCommit r12-4496 changes some define_expands and define_insns\nfor vector merge high/low short, which are altivec_vmrg[hl]h.\nThese defines are mainly for built-in function vec_merge{h,l}\nand some internal gen function needs. These functions should\nconsider endianness, taking vec_mergeh as example, as PVIPR\ndefines, vec_mergeh \"Merges the first halves (in element order)\nof two vectors\", it does note it's in element order. So it's\nmapped into vmrghh on BE while vmrglh on LE respectively.\nAlthough the mapped insns are different, as the discussion in\nPR106069, the RTL pattern should be still the same, it is\nconformed before commit r12-4496, but gets changed into\ndifferent patterns on BE and LE starting from commit r12-4496.\nSimilar to 32-bit element case in commit log of r15-1504, this\n16-bit element pattern on LE doesn't actually match what the\nunderlying insn is intended to represent, once some optimization\nlike combine does some changes basing on it, it would cause\nthe unexpected consequence. The newly constructed test case\npr106069-2.c is a typical example for this issue on element type\nshort.\n\nSo this patch is to fix the wrong RTL pattern, ensure the\nassociated RTL patterns become the same as before which can\nhave the same semantic as their mapped insns. With the\nproposed patch, the expanders like altivec_vmrghh expands\ninto altivec_vmrghh_direct_be or altivec_vmrglh_direct_le\ndepending on endianness, \"direct\" can easily show which\ninsn would be generated, _be and _le are mainly for the\ndifferent RTL patterns as endianness.\n\nCo-authored-by: Xionghu Luo \n\n\tPR target/106069\n\tPR target/115355\n\ngcc/ChangeLog:\n\n\t* config/rs6000/altivec.md (altivec_vmrghh_direct): Rename to ...\n\t(altivec_vmrghh_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.\n\t(altivec_vmrghh_direct_le): New define_insn.\n\t(altivec_vmrglh_direct): Rename to ...\n\t(altivec_vmrglh_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.\n\t(altivec_vmrglh_direct_le): New define_insn.\n\t(altivec_vmrghh): Adjust by calling gen_altivec_vmrghh_direct_be\n\tfor BE and gen_altivec_vmrglh_direct_le for LE.\n\t(altivec_vmrglh): Adjust by calling gen_altivec_vmrglh_direct_be\n\tfor BE and gen_altivec_vmrghh_direct_le for LE.\n\t(vec_widen_umult_hi_v16qi): Adjust the call to\n\tgen_altivec_vmrghh_direct by gen_altivec_vmrghh for BE\n\tand by gen_altivec_vmrglh for LE.\n\t(vec_widen_smult_hi_v16qi): Likewise.\n\t(vec_widen_umult_lo_v16qi): Adjust the call to\n\tgen_altivec_vmrglh_direct by gen_altivec_vmrglh for BE\n\tand by gen_altivec_vmrghh for LE.\n\t(vec_widen_smult_lo_v16qi): Likewise.\n\t* config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace\n\tCODE_FOR_altivec_vmrghh_direct by\n\tCODE_FOR_altivec_vmrghh_direct_be for BE and\n\tCODE_FOR_altivec_vmrghh_direct_le for LE. And replace\n\tCODE_FOR_altivec_vmrglh_direct by\n\tCODE_FOR_altivec_vmrglh_direct_be for BE and\n\tCODE_FOR_altivec_vmrglh_direct_le for LE.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/powerpc/pr106069-2.c: New test.\n\n(cherry picked from commit 812c70bf4981958488331d4ea5af8709b5321da1)","shortMessageHtmlLink":"rs6000: Fix wrong RTL patterns for vector merge high/low short on LE"}},{"before":"3e299e4278b9acb3dd1782b62aa81f4bf8703068","after":"2c8c0b3b972796158be365922c80ec624602ea44","ref":"refs/heads/releases/gcc-11","pushedAt":"2024-07-03T07:13:38.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"cc63b59e8843f049587b7a548a530f710085e577","after":"038d64f62271ddc62aa35d0a5dfd3843fdb9e6d7","ref":"refs/heads/master","pushedAt":"2024-07-03T07:13:33.000Z","pushType":"push","commitsCount":11,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"preprocessor: Create the parser before handling command-line includes [PR115312]\n\nSince r14-2893, we create a parser object in preprocess-only mode for the\npurpose of parsing #pragma while preprocessing. The parser object was\nformerly created after calling c_finish_options(), which leads to problems\non platforms that don't use stdc-predef.h (such as MinGW, as reported in\nthe PR). On such platforms, the call to c_finish_options() will process\nthe first command-line-specified include file. If that includes a PCH, then\nc-ppoutput.cc will encounter a state it did not anticipate. Fix it by\ncreating the parser prior to calling c_finish_options().\n\ngcc/c-family/ChangeLog:\n\n\tPR pch/115312\n\t* c-opts.cc (c_common_init): Call c_init_preprocess() before\n\tc_finish_options() so that a parser is available to process any\n\tincludes specified on the command line.\n\ngcc/testsuite/ChangeLog:\n\n\tPR pch/115312\n\t* g++.dg/pch/pr115312.C: New test.\n\t* g++.dg/pch/pr115312.Hs: New test.","shortMessageHtmlLink":"preprocessor: Create the parser before handling command-line includes…"}},{"before":"0b4fd672bf07e3bf8142b01125b4f8d2f14b1851","after":"cc63b59e8843f049587b7a548a530f710085e577","ref":"refs/heads/trunk","pushedAt":"2024-07-02T19:24:48.000Z","pushType":"push","commitsCount":30,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Regenerate common.opt.urls\n\nI was not aware of the requirement to regenerate the opt urls files\nwhen adding a new option until the autobuilder complained.\n\nRegenerate common.opt.urls for the -gprune-btf option added in:\n b8977d928a7a btf: add -gprune-btf option\n\ngcc/\n\t* common.opt.urls: Regenerate.","shortMessageHtmlLink":"Regenerate common.opt.urls"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEdzOQtgA","startCursor":null,"endCursor":null}},"title":"Activity · kraj/gcc"}