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1. SpinalHDL_Entry SpinalHDL_Entry Public

2. ethernet-physical-layer ethernet-physical-layer Public

   Forked from Essenceia/ethernet-physical-layer

   RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

   Tcl

3. low-latency-ethernet low-latency-ethernet Public

   Forked from BruceKevinLee/low-latency-ethernet

   RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

   Verilog

4. Nasdaq-HFT-FPGA Nasdaq-HFT-FPGA Public

   Forked from Essenceia/Nasdaq-HFT-FPGA

   RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.

   C

5. lowlatency-ethernet lowlatency-ethernet Public

   Forked from Essenceia/low-latency-ethernet

   RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

   Verilog

6. ITCH ITCH Public

   Forked from Essenceia/ITCH

   RTL implementation of the ITCH protocol decoder.

   Verilog