Fix logic for signed expect/poke

[leonardt]

(based on patch-pipefail)

Fixes the logic for compiling signed values to verilator. Basically, verilator always uses the unsigned representation as a C data type, so we need to convert all negative values into their unsigned bits representation. The logic already existed, but was too conservative (it only checked if the port was type as a signed value, but there are cases where expect a signed value on an unsigned port, such as in the case of the signed mode of the PE)

[coveralls]

Pull Request Test Coverage Report for Build 923

• 9 of 17 (52.94%) changed or added relevant lines in 3 files are covered.
• 1 unchanged line in 1 file lost coverage.
• Overall coverage decreased (-0.06%) to 76.369%

---

Changes Missing Coverage	Covered Lines	Changed/Added Lines	%
fault/verilator_target.py	8	9	88.89%
fault/system_verilog_target.py	0	7	0.0%

Files with Coverage Reduction	New Missed Lines	%
fault/system_verilog_target.py	1	16.29%

Totals
Change from base Build 919:	-0.06%
Covered Lines:	1367
Relevant Lines:	1790

---

💛 - Coveralls

[rsetaluri]

Test for this?

[Kuree]

Is it okay to merge?