Merge pull request #12 from leonardt/fun-sig-master

get inputs from signature instead of decorator

silica/__init__.py

@@ -5,7 +5,8 @@
 
 import magma as m
 from magma import Bit, zext, concat, Array, Bits, UInt
-from magma.bit_vector import BitVector
+from bit_vector import BitVector
+import bit_vector
 import operator
 
 
@@ -16,12 +17,12 @@ def __repr__(self):
 
 class Memory(list):
     def __getitem__(self, key):
-        if isinstance(key, m.bit_vector.BitVector):
+        if isinstance(key, bit_vector.BitVector):
             key = key.as_int()
         return super().__getitem__(key)
 
     def __setitem__(self, key, value):
-        if isinstance(key, m.bit_vector.BitVector):
+        if isinstance(key, bit_vector.BitVector):
             key = key.as_int()
         return super().__setitem__(key, value)
 
@@ -42,7 +43,7 @@ def zext(value, n):
     return BitVector(value, num_bits=n + value.num_bits)
 
 def add(a, b, cout=False):
-    assert isinstance(a, m.bit_vector.BitVector) and isinstance(b, m.bit_vector.BitVector)
+    assert isinstance(a, bit_vector.BitVector) and isinstance(b, bit_vector.BitVector)
     assert len(a) == len(b)
     if cout:
         width = len(a)

silica/coroutine.py

@@ -1,6 +1,5 @@
 import inspect
 
-
 class Coroutine:
     """
     Makes the initial call to __next__ upon construction to immediately
@@ -48,22 +47,19 @@ def next(self):
 def coroutine(func=None, inputs=None):
     stack = inspect.stack()
     defn_locals = stack[1].frame.f_locals
-    if inputs is not None:
-        def wrapper(func):
-            class _Coroutine(Coroutine):
-                _definition = func
-                _inputs = inputs
-                _defn_locals = defn_locals
-                _name = func.__name__
-            return _Coroutine
-        return wrapper
-    else:
+
+    inputs = inspect.getfullargspec(func).annotations
+    args = [ inputs[arg] for arg in inspect.getfullargspec(func).args ]
+    kwargs = { arg : inputs[arg] for arg in inspect.getfullargspec(func).kwonlyargs }
+
+    def wrapper():
         class _Coroutine(Coroutine):
             _definition = func
-            _inputs = {}
+            _inputs = inputs
             _defn_locals = defn_locals
             _name = func.__name__
-        return _Coroutine
+        return _Coroutine(*args, **kwargs)
+    return wrapper
 
 
 class Generator(Coroutine):

tests/test_counter.py

@@ -6,13 +6,15 @@
 from common import evaluate_circuit
 
 
-@silica.coroutine
 def SilicaCounter(width, init=0, incr=1):
-    count = bits(init, width)
-    while True:
-        O = count
-        count = count + bits(incr, width)
-        yield O
+    @silica.coroutine
+    def counter():
+        count = bits(init, width)
+        while True:
+            O = count
+            count = count + bits(incr, width)
+            yield O
+    return counter()
 
 def test_counter():
     N = 3

tests/test_detect.py

@@ -6,8 +6,8 @@
 import magma as m
 from common import evaluate_circuit
 
-@silica.coroutine(inputs={"I" : Bit})
-def SIDetect111():
+@silica.coroutine
+def SIDetect111(I : Bit):
     cnt = uint(0, 2)
     I = yield
     while True:
@@ -19,12 +19,14 @@ def SIDetect111():
         O = (cnt == 3)
         I = yield O
 
-@silica.coroutine
 def inputs_generator(inputs):
-    while True:
-        for i in inputs:
-            I = i
-            yield I
+    @silica.coroutine
+    def gen():
+        while True:
+            for i in inputs:
+                I = i
+                yield I
+    return gen()
 
 def test_detect111():
     detect = SIDetect111()

tests/test_fifo.py

@@ -7,8 +7,8 @@
 import magma as m
 
 
-@si.coroutine(inputs={"wdata": si.Bits(4), "wen": si.Bit, "ren": si.Bit})
-def SilicaFifo():
+@si.coroutine
+def SilicaFifo(wdata: si.Bits(4), wen: si.Bit, ren: si.Bit):
     buffer = memory(4, 4)
     raddr = uint(0, 3)
     waddr = uint(0, 3)
@@ -72,14 +72,16 @@ def SilicaFifo():
     {'wdata': 14, 'wen': 1, 'ren': 1, 'rdata': 10, 'full': False, 'empty': False, 'buffer': [14, 10, 11, 12], 'raddr': 6, 'waddr': 1},
 ]
 
-@si.coroutine
 def inputs_generator(N):
-    while True:
-        for trace in expected_trace:
-            wdata = bits(trace["wdata"], N)
-            wen = bool(trace["wen"])
-            ren = bool(trace["ren"])
-            yield wdata, wen, ren
+    @si.coroutine
+    def gen():
+        while True:
+            for trace in expected_trace:
+                wdata = bits(trace["wdata"], N)
+                wen = bool(trace["wen"])
+                ren = bool(trace["ren"])
+                yield wdata, wen, ren
+    return gen()
 
 def test_fifo():
     fifo = SilicaFifo()

tests/test_lbmem.py

@@ -60,41 +60,45 @@ def DrainingState(lbmem_width, depth, lbmem, raddr, waddr, wdata, wen):
     valid = bit(0)
     return waddr, raddr
 
-@si.coroutine(inputs={"wdata": si.Bits(8), "wen": si.Bit})
 def SILbMem(depth=64, lbmem_width=8):
-    lbmem = memory(depth, lbmem_width)
-    waddr = uint(0, eval(math.ceil(math.log2(depth))))
-    count = uint(0, 3)
-    wdata, wen = yield
-    while True:
-        while (count < uint(7, 3)) | ~wen:
-            rdata = lbmem[waddr - uint(count, 6)]
-            valid = bit(0)
-            if wen:
-                lbmem[waddr] = wdata
-                count = count + 1
-                waddr = waddr + 1
-            wdata, wen = yield rdata, valid
-        lbmem[waddr] = wdata
-        while count > 0:
-            valid = bit(1)
-            rdata = lbmem[waddr - uint(count, 6)]
-            if ~wen:
-                count = count - 1
-            if wen:
-                lbmem[waddr] = wdata
-                waddr = waddr + 1
-            wdata, wen = yield rdata, valid
+    @si.coroutine
+    def mem(wdata : si.Bits(8), wen : si.Bit):
+        lbmem = memory(depth, lbmem_width)
+        waddr = uint(0, eval(math.ceil(math.log2(depth))))
+        count = uint(0, 3)
+        wdata, wen = yield
+        while True:
+            while (count < uint(7, 3)) | ~wen:
+                rdata = lbmem[waddr - uint(count, 6)]
+                valid = bit(0)
+                if wen:
+                    lbmem[waddr] = wdata
+                    count = count + 1
+                    waddr = waddr + 1
+                wdata, wen = yield rdata, valid
+            lbmem[waddr] = wdata
+            while count > 0:
+                valid = bit(1)
+                rdata = lbmem[waddr - uint(count, 6)]
+                if ~wen:
+                    count = count - 1
+                if wen:
+                    lbmem[waddr] = wdata
+                    waddr = waddr + 1
+                wdata, wen = yield rdata, valid
 
-    # while True:
-    #     waddr = yield from FillingState(lbmem_width, depth, lbmem, raddr, waddr, wdata, wen)
-    #     waddr, raddr = yield from DrainingState(lbmem_width, depth, lbmem, raddr, waddr, wdata, wen)
+        # while True:
+        #     waddr = yield from FillingState(lbmem_width, depth, lbmem, raddr, waddr, wdata, wen)
+        #     waddr, raddr = yield from DrainingState(lbmem_width, depth, lbmem, raddr, waddr, wdata, wen)
+    return mem()
 
-@si.coroutine
 def inputs_generator(inputs):
-    while True:
-        for wdata, wen in inputs:
-            yield wdata, wen
+    @si.coroutine
+    def gen():
+        while True:
+            for wdata, wen in inputs:
+                yield wdata, wen
+    return gen()
 
 def test_lbmem():
     lbmem = SILbMem()

tests/test_piso.py

@@ -12,8 +12,8 @@
 
 
 def DefinePISO(n):
-    @silica.coroutine(inputs={"PI": silica.Bits(n), "SI": silica.Bit, "LOAD": silica.Bit})
-    def SIPISO():
+    @silica.coroutine
+    def SIPISO(PI: silica.Bits(n), SI: silica.Bit, LOAD: silica.Bit):
         values = bits(0, n)
         # O = values[-1]
         PI, SI, LOAD = yield
@@ -31,18 +31,20 @@ def SIPISO():
     return SIPISO
 
 
-@silica.coroutine
 def inputs_generator(message):
-    while True:
-        for byte in message:
-            PI = [bool(x) for x in [0] + int2seq(byte) + [1]]
-            SI = False
-            LOAD = True
-            yield PI, SI, LOAD
-            for i in range(10):
-                LOAD = False
-                PI = [bool(x) for x in int2seq(0xFF, 10)]
+    @silica.coroutine
+    def gen():
+        while True:
+            for byte in message:
+                PI = [bool(x) for x in [0] + int2seq(byte) + [1]]
+                SI = False
+                LOAD = True
                 yield PI, SI, LOAD
+                for i in range(10):
+                    LOAD = False
+                    PI = [bool(x) for x in int2seq(0xFF, 10)]
+                    yield PI, SI, LOAD
+    return gen()
 
 
 def test_PISO():

tests/test_serializer.py

@@ -7,8 +7,8 @@
 import fault
 
 
-@coroutine(inputs={"I0" : Bits(16), "I1" : Bits(16), "I2" : Bits(16), "I3" : Bits(16)})
-def Serializer4():
+@coroutine
+def Serializer4(I0 : Bits(16), I1 : Bits(16), I2 : Bits(16), I3 : Bits(16)):
     # data = [bits(0, 16) for _ in range(3)]
     data0 = bits(0, 16)
     data1 = bits(0, 16)
@@ -33,15 +33,17 @@ def Serializer4():
         #     I0, I1, I2, I3 = yield O
 
 
-@coroutine
 def inputs_generator(inputs):
-    while True:
-        for i in inputs:
-            I = [BitVector(x, 16) for x in i]
-            yield I
-            for _ in range(3):
-                I = [BitVector((_ * len(i)) + j, 16) for j in range(len(i))]
+    @coroutine
+    def gen():
+        while True:
+            for i in inputs:
+                I = [BitVector(x, 16) for x in i]
                 yield I
+                for _ in range(3):
+                    I = [BitVector((_ * len(i)) + j, 16) for j in range(len(i))]
+                    yield I
+    return gen()
 
 inputs = [[4,5,6,7],[10,16,8,3]]
 
@@ -69,7 +71,7 @@ def test_ser4():
             tester.expect(serializer_si.O, I[i + 1])
             tester.step(1)
     tester.compile_and_run(target="verilator", directory="tests/build",
-                           flags=['-Wno-fatal'])
+                           flags=['-Wno-fatal', '--trace'])
 
 
     shutil.copy("verilog/serializer.v", "tests/build/serializer_verilog.v")
@@ -79,7 +81,7 @@ def test_ser4():
 
     verilog_tester = tester.retarget(serializer_verilog, serializer_verilog.CLK)
     verilog_tester.compile_and_run(target="verilator", directory="tests/build",
-                                   flags=['-Wno-fatal'])
+                                   flags=['-Wno-fatal', '--trace'])
 
     if __name__ == '__main__':
         print("===== BEGIN : SILICA RESULTS =====")

tests/test_tff.py

@@ -6,14 +6,17 @@
 from common import evaluate_circuit
 
 
-@silica.coroutine(inputs={"I": silica.Bit})
 def TFF(init=0):
-    state = bit(init)
-    I = yield
-    while True:
-        O = state
-        state = I ^ state
-        I = yield O
+    @silica.coroutine
+    def tff(I : silica.Bit):
+        state = bit(init)
+        I = yield
+        while True:
+            O = state
+            state = I ^ state
+            I = yield O
+
+    return tff()
 
 
 def test_TFF():

tests/test_uart.py

@@ -22,8 +22,8 @@
 #             tx = 1
 #             yield
 
-@silica.coroutine(inputs={"data": silica.Bits(8), "valid": silica.Bit})
-def uart_transmitter():
+@silica.coroutine
+def uart_transmitter(data : silica.Bits(8), valid : silica.Bit):
     data, valid = yield
     while True:
         if valid: