Add initial MNT Reform Kintex-7 module (RKX7) support with Clk, UART …

…and DDR3.

Compiles but untested on hardware.

litex_boards/platforms/mnt_rkx7.py

@@ -0,0 +1,78 @@
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from litex.build.generic_platform import *
+from litex.build.xilinx import XilinxPlatform
+from litex.build.openocd import OpenOCD
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # Clk / Rst.
+    ("clk100", 0, Pins("AA10"), IOStandard("LVCMOS15")),
+
+    # Serial.
+    ("serial", 0,
+        Subsignal("tx", Pins("D15")),
+        Subsignal("rx", Pins("C18")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # DDR3 SDRAM.
+    ("ddram", 0,
+        Subsignal("a",       Pins(
+            "AC8 AA7 AA8 AF7 AE7 AC11 V9 Y10",
+            "AB11 Y7  Y8 V11  V8  W11 Y11 V7 "),
+            IOStandard("SSTL15")),
+        Subsignal("ba",      Pins("AC7 AB7 AB9"), IOStandard("SSTL15")),
+        Subsignal("ras_n",   Pins("AA9"), IOStandard("SSTL15")),
+        Subsignal("cas_n",   Pins("AD8"), IOStandard("SSTL15")),
+        Subsignal("we_n",    Pins("AC9"), IOStandard("SSTL15")),
+        Subsignal("cs_n",    Pins("AD9"), IOStandard("SSTL15")),
+        Subsignal("dm",      Pins(
+            "U6 Y3 AB6 AD4"),
+            IOStandard("SSTL15")),
+        Subsignal("dq",      Pins(
+            " V4  W3  U5  U1  U7  U2  V6  V3",
+            " Y2  Y1 AA3  V2 AC2  W1 AB2  V1",
+            "AA4 AB4 AC4 AC3 AC6  Y6  Y5 AD6",
+            "AD1 AE1 AE3 AE2 AE6 AE5 AF3 AF2"),
+            IOStandard("SSTL15_T_DCI")),
+        Subsignal("dqs_p",   Pins("W6 AB1 AA5 AF5"),
+            IOStandard("DIFF_SSTL15")),
+        Subsignal("dqs_n",   Pins("W5 AC1 AB5 AF4"),
+            IOStandard("DIFF_SSTL15")),
+        Subsignal("clk_p",   Pins("W10"),  IOStandard("DIFF_SSTL15")),
+        Subsignal("clk_n",   Pins("W9"),   IOStandard("DIFF_SSTL15")),
+        Subsignal("cke",     Pins("AB12"), IOStandard("SSTL15")),
+        Subsignal("odt",     Pins("AC12"), IOStandard("SSTL15")),
+        Subsignal("reset_n", Pins("AA2"),  IOStandard("LVCMOS15")),
+        Misc("SLEW=FAST"),
+        Misc("VCCAUX_IO=HIGH")
+    ),
+]
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors = []
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(XilinxPlatform):
+    default_clk_name   = "clk100"
+    default_clk_period = 1e9/100e6
+
+    def __init__(self):
+        XilinxPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain="vivado")
+
+    def create_programmer(self):
+        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
+
+    def do_finalize(self, fragment):
+        XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
+        self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")

litex_boards/targets/mnt_rkx7.py

@@ -0,0 +1,95 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import os
+import argparse
+
+from migen import *
+
+from litex_boards.platforms import mnt_rkx7
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+from litedram.modules import MT41K512M16 # FIXME: IS43TR16512B
+from litedram.phy import s7ddrphy
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
+        self.clock_domains.cd_sys    = ClockDomain()
+        self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
+        self.clock_domains.cd_idelay = ClockDomain()
+
+        # # #
+
+        self.submodules.pll = pll = S7MMCM(speedgrade=-2)
+        self.comb += pll.reset.eq(self.rst)
+        pll.register_clkin(platform.request("clk100"), 100e6)
+        pll.create_clkout(self.cd_sys,    sys_clk_freq)
+        pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
+        pll.create_clkout(self.cd_idelay, 200e6)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
+
+        self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+        platform = mnt_rkx7.Platform()
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq,
+            ident          = "LiteX SoC on MNT-RKX7",
+            ident_version  = True,
+            **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
+                memtype      = "DDR3",
+                nphases      = 4,
+                sys_clk_freq = sys_clk_freq)
+            self.add_sdram("sdram",
+                phy           = self.ddrphy,
+                module        = MT41K512M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192),
+            )
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on MNT-RKX7")
+    parser.add_argument("--build",        action="store_true", help="Build bitstream")
+    parser.add_argument("--load",         action="store_true", help="Load bitstream")
+    parser.add_argument("--sys-clk-freq", default=100e6,       help="System clock frequency (default: 100MHz)")
+    builder_args(parser)
+    soc_core_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(
+        sys_clk_freq   = int(float(args.sys_clk_freq)),
+        **soc_core_argdict(args)
+    )
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+
+if __name__ == "__main__":
+    main()