Hackaday Badge : optimize performance #35
Comments
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@enjoy-digital thanks, it seems that boot to login prompt is 48 seconds faster. Dropbear SSH starts after 258 seconds on the optimized version versus 306 seconds in the original version. Here is it getting to login: I have uploaded asciinema: versus the original asciinema before optimization: The original version login prompt: |
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Thanks for the results, so you also have the ~10% performance gain. I'll continue looking at the bottlenecks next week if possible. |
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@pdp7: enjoy-digital/litedram@721c84b and enjoy-digital/litex@39ce39a should give interesting boot time speed up on the Hackaday badge :) If you want to try, you can rebuild with upstream LiteX/LiteDRAM or just use the bitstream attached: |
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@enjoy-digital WOW! much faster! It gets to login in 28 seconds (previous version was 258 seconds). Recording: Text: |
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Great :) thanks for testing. That would also be interesting to test with with |
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@enjoy-digital thanks, that is even faster by about 3 seconds, so a 12% speed-up. pdp7@x1:~/dev/enjoy/litex$ git diff
diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 2535e85d..29873a8d 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -26,7 +26,7 @@ class SoCSDRAM(SoCCore):
}
csr_map.update(SoCCore.csr_map)
- def __init__(self, platform, clk_freq, l2_size=8192, l2_data_width=128, **kwargs):
+ def __init__(self, platform, clk_freq, l2_size=8192, l2_data_width=256, **kwargs):
SoCCore.__init__(self, platform, clk_freq, **kwargs)
if not self.integrated_main_ram_size:
if self.cpu_type is not None and self.csr_data_width > 32:boot log: |
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@pdp7: thanks, |
enjoy-digital
changed the title
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While the kernel boots in under 30 seconds, it currently it takes about 2 minutes to load the kernel Image and rootfs.cpio:
The badge and cartridge both have: @mithro suggested I try to use the built-in Flash to store those, rather than load over serial. @enjoy-digital @xobs @gregdavill @jcreedon @mwelling: |
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@pdp7 you can look at the Arty. It was working at some point but i'm not sure the linux binaries are still fitting in the SPI Flash. The other thing is that you now need to make sure to append length and CRC with https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/mkmscimg.py before writing the images. You can find the flash offsets here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/boot.c#L411-L414 |
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The first thing to do is to add the Flash pins to your board, similar to https://github.com/litex-hub/litex-boards/blob/master/litex_boards/official/platforms/versa_ecp5.py#L47-L51. Then add "spiflash" to the capabilities: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/make.py#L181 and test the build. On hardware, you can then check if the SPI Flash is working correctly with the mr/fe/fw commands of the BIOS: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/main.c#L345-L350 It's possible you will have to adjust: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py#L110 |
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@enjoy-digital thank for you for insights. and I'm trying this diff: diff --git a/make.py b/make.py
index f63e469..44574c2 100755
--- a/make.py
+++ b/make.py
@@ -163,9 +163,12 @@ class ULX3S(Board):
# HADBadge support ---------------------------------------------------------------------------------
class HADBadge(Board):
+ SPIFLASH_PAGE_SIZE = 256
+ SPIFLASH_SECTOR_SIZE = 64*kB
def __init__(self):
from litex_boards.targets import hadbadge
- Board.__init__(self, hadbadge.BaseSoC, {"serial"})
+ Board.__init__(self, hadbadge.BaseSoC, {"serial", "spiflash"})
+ #Board.__init__(self, arty.EthernetSoC, {"serial", "ethernet", "spiflash", "leds", "rgb_led", "switches", "spi", "i2c", "xadc", "icap_bit"})
def load(self):
os.system("dfu-util --alt 2 --download build/hadbadge/gateware/top.bit --reset")
diff --git a/soc_linux.py b/soc_linux.py
index 98f6d7e..c76f373 100644
--- a/soc_linux.py
+++ b/soc_linux.py
@@ -63,10 +63,10 @@ def SoCLinux(soc_cls, **kwargs):
def add_spi_flash(self):
# TODO: add spiflash1x support
- spiflash_pads = self.platform.request("spiflash4x")
+ spiflash_pads = self.platform.request("spiflash")
self.submodules.spiflash = SpiFlash(
spiflash_pads,
- dummy=11,
+ dummy=8,
div=2,
with_bitbang=True,
endianness=self.cpu.endianness)From It looks like I can read the flash ok: |
thanks, do you know what tool I would use to write the files to flash? |
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You can try to use lxterm with |
Thanks, I'm trying: and: followed by more garbage output. I think I must have something not right in the configuration. |
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As i was explaining in #35 (comment), the files will first need to be patched with https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/mkmscimg.py to add the CRC and length and be sure to use the same offsets than in |
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@enjoy-digital thank you, I ran the mkmscimg.py and created .fbi files: Do you know if @mithro is thinking that would overwrite the gateware. UPDATE: that does seem to be what is happening. The gateware disappears and I have to run |
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I see that: so I added 0x00400000 to the addresses in images.json.fbi: |
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I'm trying to get the Hackaday Badge to boot from the SPI flash as it takes 2 mintues to load the kernel and rootfs over serial. Repo version: Repo diff: pdp7@x1:~/dev/enjoy/linux-on-litex-vexriscv/buildroot$ git diff
diff --git a/make.py b/make.py
index e472c25..27dcdd9 100755
--- a/make.py
+++ b/make.py
@@ -179,8 +179,8 @@ class ULX3S(Board):
# HADBadge support ---------------------------------------------------------------------------------
class HADBadge(Board):
- SPIFLASH_PAGE_SIZE = 256 # CHECKME
- SPIFLASH_SECTOR_SIZE = 64*kB # CHECKME
+ SPIFLASH_PAGE_SIZE = 256
+ SPIFLASH_SECTOR_SIZE = 64*kB
SPIFLASH_DUMMY_CYCLES = 8
def __init__(self):
from litex_boards.targets import hadbadge
diff --git a/soc_linux.py b/soc_linux.py
index ecf875b..df90848 100644
--- a/soc_linux.py
+++ b/soc_linux.py
@@ -104,7 +104,8 @@ def SoCLinux(soc_cls, **kwargs):
def add_spi_flash(self, dummy_cycles):
# TODO: add spiflash1x support
- spiflash_pads = self.platform.request("spiflash4x")
+ spiflash_pads = self.platform.request("spiflash")
+ #spiflash_pads = self.platform.request("spiflash4x")
self.submodules.spiflash = SpiFlash(
spiflash_pads,
dummy = dummy_cycles,Generating the fbi files: |
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I added a prefix of 0x00010000 so flashing these files won't overwrite the gateware. I then try to flash the files, but LiteX BIOS prints junk. @mithro @enjoy-digital any ideas? |
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@pdp7: the default addresses for flashing are: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/boot.c#L411-L414 (+ your SPI Flash offset). You can modify it, but it needs to be consistent between the BIOS and flashing script. At startup, the BIOS will then copy the data from SPI Flash to the SDRAM and Emulator RAM and jump to Emulator RAM. In your case, it seems you are flashing the Linux images (not using the default addresses) but also "flashing" the emulator.bin to the Emulator RAM which will not work. |
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I'm going to close this issue and address the effort to boot from flash in #42 |
Related to comments in PR #31 (comment)
The performance of the ECP5 Hackaday Badge with 32MB SDRAM is "painfully" slow.
@mithro suggested there could be some issue with the configuration.
@enjoy-digital has attempted some optimizations:
#31 (comment)
I will measure if the boot time improve
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