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git-subtree-dir: pythondata_cpu_serv/verilog
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pythondata_cpu_serv/verilog/.gitmodules

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+[submodule "zephyr"]
+	path = zephyr
+	url = https://github.com/olofk/zephyr
+	branch = serv

pythondata_cpu_serv/verilog/LICENSE

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+ISC License
+
+Copyright 2019, Olof Kindgren
+
+Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

pythondata_cpu_serv/verilog/README.md

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+<img align="right" src="https://svg.wavedrom.com/{signal:[{wave:'0.P...'},{wave:'023450',data:'S E R V'}]}"/>
+
+# SERV
+
+SERV is an award-winning bit-serial RISC-V core
+
+## Prerequisites
+
+Create a directory to keep all the different parts of the project together. We
+will refer to this directory as `$SERV` from now on.
+
+Download the main serv repo
+
+`cd $SERV && git clone https://github.com/olofk/serv`
+
+Install FuseSoC
+
+`pip install fusesoc`
+
+Initialize the FuseSoC standard libraries
+
+`fusesoc init`
+
+Create a workspace directory for FuseSoC
+
+`mkdir $SERV/workspace`
+
+Register the serv repo as a core library
+
+`cd $SERV/workspace && fusesoc library add serv $SERV`
+
+Check that the CPU passes the linter
+
+`cd $SERV/workspace && fusesoc run --target=lint serv`
+
+## Running test software
+
+Build and run the single threaded zephyr hello world example with verilator (should be stopped with Ctrl-C):
+
+    cd $SERV/workspace
+    fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/serv/sw/zephyr_hello.hex
+
+..or... the multithreaded version
+
+    fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/serv/sw/zephyr_hello_mt.hex --memsize=16384
+
+...or... the philosophers example
+
+    fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/serv/sw/zephyr_phil.hex --memsize=32768
+
+...or... the synchronization example
+
+    fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/serv/sw/zephyr_sync.hex --memsize=16384
+
+Other applications can be tested by compiling and converting to bin and then hex e.g. with makehex.py found in `$SERV/serv/riscv-target/serv`
+
+## Run the compliance tests
+
+Build the verilator model (if not already done)
+
+`cd $SERV/workspace && fusesoc run --target=verilator_tb --setup --build servant`
+
+Download the tests repo
+
+`cd $SERV && git clone https://github.com/riscv/riscv-compliance`
+
+Run the compliance tests
+
+`cd $SERV/riscv-compliance && make TARGETDIR=$SERV/serv/riscv-target RISCV_TARGET=serv RISCV_DECICE=rv32i RISCV_ISA=rv32i TARGET_SIM=$SERV/workspace/build/servant_1.0.1/verilator_tb-verilator/Vservant_sim`
+
+## Run on hardware
+
+The servant SoC has been ported to a number of different FPGA boards. To see all currently supported targets run
+
+    fusesoc core show servant
+
+By default, these targets have the program memory preloaded with a small Zephyr hello world example that writes its output on a UART pin. Don't forget to install the appropriate toolchain (e.g. icestorm, Vivado, Quartus...) and add to your PATH
+
+Some targets also depend on functionality in the FuseSoC base library (fusesoc-cores). Running `fusesoc library list` should tell you if fusesoc-cores is already available. If not, add it to your workspace with
+
+    fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores
+
+Now we're ready to build. Note, for all the cases below, it's possible to run with `--memfile=$SERV/sw/blinky.hex`
+(or any other suitable program) as the last argument to preload the LED blink example
+instead of hello world.
+
+### TinyFPGA BX
+
+Pin A6 is used for UART output with 115200 baud rate.
+
+    cd $SERV/workspace
+    fusesoc run --target=tinyfpga_bx servant
+    tinyprog --program build/servant_1.0.1/tinyfpga_bx-icestorm/servant_1.0.1.bin
+
+### Icebreaker
+
+Pin 9 is used for UART output with 57600 baud rate.
+
+    cd $SERV/workspace
+    fusesoc run --target=icebreaker servant
+
+### Arty A7 35T
+
+Pin D10 (uart_rxd_out) is used for UART output with 57600 baud rate (to use
+blinky.hex change D10 to H5 (led[4]) in data/arty_a7_35t.xdc).
+
+    cd $SERV/workspace
+    fusesoc run --target=arty_a7_35t servant
+
+### Alhambra II
+
+Pin 61 is used for UART output with 38400 baud rate (note that it works with non-standard 43200 value too). This pin is connected to a FT2232H chip in board, that manages the communications between the FPGA and the computer.
+
+    cd $SERV/workspace
+    fusesoc run --target=alhambra servant
+    iceprog -d i:0x0403:0x6010:0 build/servant_1.0.1/alhambra-icestorm/servant_1.0.1.bin
+
+## Other targets
+
+The above targets are run on the servant SoC, but there are some targets defined for the CPU itself. Verilator can be run in lint mode to check for design problems by running
+
+    fusesoc run --target=lint serv
+
+It's also possible to just synthesise for different targets to check resource usage and such. To do that for the iCE40 devices, run
+
+    fusesoc run --tool=icestorm serv --pnr=none
+
+...or to synthesize with vivado for Xilinx targets, run
+
+    fusesoc run --tool=vivado serv --pnr=none
+
+This will synthesize for the default Vivado part. To synthesise for a specific device, run e.g.
+
+    fusesoc run --tool=vivado serv --pnr=none --part=xc7a100tcsg324-1
+
+
+## Good to know
+
+Don't feed serv any illegal instructions after midnight. Many logic expressions are hand-optimized using the old-fashioned method with Karnaugh maps on paper, and shamelessly take advantage of the fact that some opcodes aren't supposed to appear. As serv was written with 4-input LUT FPGAs as target, and opcodes are 5 bits, this can save quite a bit of resources in the decoder.
+
+The bus interface is kind of Wishbone, but with most signals removed. There's an important difference though. Don't send acks on the instruction or data buses unless serv explicitly asks for something by raising its cyc signal. Otherwise serv becomes very confused.
+
+Don't go changing the clock frequency on a whim when running Zephyr. Or well, it's ok I guess, but since the UART is bitbanged, this will change the baud rate as well. As of writing, the UART is running at 115200 baud rate when the CPU is 32 MHz. There are two NOPs in the driver to slow it down a bit, so if those are removed I think it could achieve baud rate 115200 on a 24MHz clock.. in case someone wants to try
+
+## TODO
+
+- Applications have to be preloaded to RAM at compile-time
+- Store bootloader and register file together in a RAM
+- Make it faster and smaller

pythondata_cpu_serv/verilog/bench/servant_sim.v

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+`default_nettype none
+module servant_sim
+  (input wire  wb_clk,
+   input wire  wb_rst,
+   output wire q);
+
+   parameter memfile = "";
+   parameter memsize = 8192;
+   parameter with_csr = 1;
+
+   reg [1023:0] firmware_file;
+   initial
+     if ($value$plusargs("firmware=%s", firmware_file)) begin
+	$display("Loading RAM from %0s", firmware_file);
+	$readmemh(firmware_file, dut.ram.mem);
+     end
+
+   servant
+     #(.memfile  (memfile),
+       .memsize  (memsize),
+       .sim      (1),
+       .with_csr (with_csr))
+   dut(wb_clk, wb_rst, q);
+
+endmodule

pythondata_cpu_serv/verilog/bench/servant_tb.cpp

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+#include <stdint.h>
+#include <signal.h>
+
+#include "verilated_vcd_c.h"
+#include "Vservant_sim.h"
+
+using namespace std;
+
+static bool done;
+
+vluint64_t main_time = 0;       // Current simulation time
+// This is a 64-bit integer to reduce wrap over issues and
+// allow modulus.  You can also use a double, if you wish.
+
+double sc_time_stamp () {       // Called by $time in Verilog
+  return main_time;           // converts to double, to match
+  // what SystemC does
+}
+
+void INThandler(int signal)
+{
+	printf("\nCaught ctrl-c\n");
+	done = true;
+}
+
+typedef struct {
+  bool last_value;
+} gpio_context_t;
+
+void do_gpio(gpio_context_t *context, bool gpio) {
+  if (context->last_value != gpio) {
+    context->last_value = gpio;
+    printf("%lu output q is %s\n", main_time, gpio ? "ON" : "OFF");
+  }
+}
+
+typedef struct {
+  uint8_t state;
+  char ch;
+  uint32_t baud_t;
+  vluint64_t last_update;
+} uart_context_t;
+
+void uart_init(uart_context_t *context, uint32_t baud_rate) {
+  context->baud_t = 1000*1000*1000/baud_rate;
+  context->state = 0;
+}
+
+void do_uart(uart_context_t *context, bool rx) {
+  if (context->state == 0) {
+    if (rx)
+      context->state++;
+  }
+  else if (context->state == 1) {
+    if (!rx) {
+      context->last_update = main_time + context->baud_t/2;
+      context->state++;
+    }
+  }
+  else if(context->state == 2) {
+    if (main_time > context->last_update) {
+      context->last_update += context->baud_t;
+      context->ch = 0;
+      context->state++;
+    }
+  }
+  else if (context->state < 11) {
+    if (main_time > context->last_update) {
+      context->last_update += context->baud_t;
+      context->ch |= rx << (context->state-3);
+      context->state++;
+    }
+  }
+  else {
+    if (main_time > context->last_update) {
+      context->last_update += context->baud_t;
+      putchar(context->ch);
+      context->state=1;
+    }
+  }
+}
+
+int main(int argc, char **argv, char **env)
+{
+  vluint64_t sample_time = 0;
+	uint32_t insn = 0;
+	uint32_t ex_pc = 0;
+	int baud_rate = 0;
+
+	gpio_context_t gpio_context;
+	uart_context_t uart_context;
+	Verilated::commandArgs(argc, argv);
+
+	Vservant_sim* top = new Vservant_sim;
+
+	const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate=");
+	if (arg[0]) {
+	  baud_rate = atoi(arg+15);
+	  if (baud_rate) {
+	    uart_init(&uart_context, baud_rate);
+	  }
+	}
+
+	VerilatedVcdC * tfp = 0;
+	const char *vcd = Verilated::commandArgsPlusMatch("vcd=");
+	if (vcd[0]) {
+	  Verilated::traceEverOn(true);
+	  tfp = new VerilatedVcdC;
+	  top->trace (tfp, 99);
+	  tfp->open ("trace.vcd");
+	}
+
+	signal(SIGINT, INThandler);
+
+	vluint64_t timeout = 0;
+	const char *arg_timeout = Verilated::commandArgsPlusMatch("timeout=");
+	if (arg_timeout[0])
+	  timeout = atoi(arg_timeout+9);
+
+	vluint64_t vcd_start = 0;
+	const char *arg_vcd_start = Verilated::commandArgsPlusMatch("vcd_start=");
+	if (arg_vcd_start[0])
+	  vcd_start = atoi(arg_vcd_start+11);
+
+	bool dump = false;
+	top->wb_clk = 1;
+	bool q = top->q;
+	while (!(done || Verilated::gotFinish())) {
+	  if (tfp && !dump && (main_time > vcd_start)) {
+	    dump = true;
+	  }
+	  top->wb_rst = main_time < 100;
+	  top->eval();
+	  if (dump)
+	    tfp->dump(main_time);
+	  if (baud_rate)
+	    do_uart(&uart_context, top->q);
+	  else
+	    do_gpio(&gpio_context, top->q);
+
+	  if (timeout && (main_time >= timeout)) {
+	    printf("Timeout: Exiting at time %lu\n", main_time);
+	    done = true;
+	  }
+
+	  top->wb_clk = !top->wb_clk;
+	  main_time+=31.25;
+
+	}
+	if (tfp)
+	  tfp->close();
+	exit(0);
+}

pythondata_cpu_serv/verilog/bench/servant_tb.v

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+`default_nettype none
+module servant_tb;
+
+   parameter memfile = "";
+   parameter memsize = 8192;
+   parameter with_csr = 1;
+
+   reg wb_clk = 1'b0;
+   reg wb_rst = 1'b1;
+
+   always  #31 wb_clk <= !wb_clk;
+   initial #62 wb_rst <= 1'b0;
+
+   vlog_tb_utils vtu();
+
+   uart_decoder #(57600) uart_decoder (q);
+
+   servant_sim
+     #(.memfile  (memfile),
+       .memsize  (memsize),
+       .with_csr (with_csr))
+   dut(wb_clk, wb_rst, q);
+
+endmodule

pythondata_cpu_serv/verilog/bench/uart_decoder.v

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+module uart_decoder
+  #(parameter BAUD_RATE = 115200)
+   (input rx);
+
+   localparam T = 1000000000/BAUD_RATE;
+
+   integer i;
+   reg [7:0] ch;
+
+   initial forever begin
+      @(negedge rx);
+      #(T/2) ch = 0;
+      for (i=0;i<8;i=i+1)
+	#T ch[i] = rx;
+      $write("%c",ch);
+      $fflush;
+   end
+endmodule

pythondata_cpu_serv/verilog/data/alhambra.pcf

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+# 12 MHz clock
+set_io i_clk        49
+
+# RS232
+set_io q 61