info.yaml

# Tiny Tapeout project information
project:
  title:        "RO-based Physically Unclonable Function (PUF)"      # Project title
  author:       "Pablo Aravena"      # Your name
  discord:      "litneet64"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)"      # One line description of what your project does
  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
  clock_hz:     10_000_000       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_litneet64_ro_puf"
  
  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
  source_files:       
    - "arbiter.v" 
    - "counter.v"
    - "mux_16.v"
    - "ring_osc.v"
    - "puf_bit.v"
    - "tt_um_ro_puf.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "challenge bit 1"
  ui[1]: "challenge bit 2"
  ui[2]: "challenge bit 3"
  ui[3]: "challenge bit 4"
  ui[4]: "challenge bit 5"
  ui[5]: "challenge bit 6"
  ui[6]: "challenge bit 7"
  ui[7]: "challenge bit 8"

  # Outputs
  uo[0]: "response bit 1"
  uo[1]: "response bit 2"
  uo[2]: "response bit 3"
  uo[3]: "response bit 4"
  uo[4]: "response bit 5"
  uo[5]: "response bit 6"
  uo[6]: "response bit 7"
  uo[7]: "response bit 8"

  # Bidirectional pins
  uio[0]: ""
  uio[1]: ""
  uio[2]: ""
  uio[3]: ""
  uio[4]: ""
  uio[5]: ""
  uio[6]: ""
  uio[7]: ""

# Do not change!
yaml_version: 6