[Seq] Add clock gate operation #5082
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| @@ -24,6 +24,29 @@ using namespace mlir; | |||
| using namespace circt; | |||
| using namespace seq; | |||
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| /// Determine the integer value of a constant operand. | |||
| static std::optional<APInt> getConstantInt(Attribute operand) { | |||
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It feels like these are useful in general (and likely copied from combfolds). Would it make sense to put them in a shared utility header?
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I didn't find any such op in the comb folds yet. But we should definitely add such a header to reduce code duplication.
Add a `seq.clock_gate` operation that represents a safe, glitchless gating of a clock. It isn't totally clear to me which dialect this op best fits into, but given that it interacts with clocks and contains an internal storage element to avoid glitching, Seq seems like a good fit. This commit merely adds the op, canonicalizations, and basic tests. It isn't used or lowered yet. I imagine that the `LowerSeqToSV` pass would be able to lower this clock gate either to an extmodule or to an inline simulation model later.
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| OpFoldResult ClockGateOp::fold(FoldAdaptor adaptor) { | ||
| // Forward the clock if one of the enables is always true. | ||
| if (isConstantOne(adaptor.getEnable()) || | ||
| isConstantOne(adaptor.getTestEnable())) |
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Does this need to check for existence of the enable first?
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That's done in isConstantOne. The adaptor will return null if the enable isn't there, and the function handles that case.
| // CHECK-NEXT: %alwaysOff1 = hw.wire %false sym @alwaysOff1 | ||
| // CHECK-NEXT: %alwaysOff2 = hw.wire %false sym @alwaysOff2 | ||
| %1 = seq.clock_gate %clock, %false | ||
| %2 = seq.clock_gate %clock, %false, %false |
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Using true for the enable would provide more coverage.
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There are separate always-on tests for the constant true case. The problem here is if I pass one of the enables as constant true, it will just make the clock gate fold away (the enables are ORed).
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Actual clock gate cells have DTF signals eg a test enable override. Does this op include space for that...? (Did not try to read the code but curious your thoughts on this) |
Yes! The op has an optional |
Add a
seq.clock_gateoperation that represents a safe, glitchless gating of a clock. It isn't totally clear to me which dialect this op best fits into, but given that it interacts with clocks and contains an internal storage element to avoid glitching, Seq seems like a good fit.This commit merely adds the op, canonicalizations, and basic tests. It isn't used or lowered yet. I imagine that the
LowerSeqToSVpass would be able to lower this clock gate either to an extmodule or to an inline simulation model later.