[Seq] Add a preset value to allow fir registers to be preset

[nandor]

See RationaleSeq.md

[seldridge]

A slightly different formulation has the preset subsume the randomized preset value. I.e., there is a preset <value | "random"> and the presence of the "random" flavor is what produces the existing lowering. If no preset is specified, then this is equivalent to disabling randomization.

The main benefit of this is that it seems odd to lump eliding presets under disabling randomization and this provides a way out of it.

[nandor]

I agree, we should introduce "preset random", but that requires a lot of test adjusments and it slightly exceeds the scope of what I need to do now. I adjusted the docs a bit to better reflect that.

[uenoku]

Async regreset is currently conditionally assigned to a reset value in the initial block so what's the expected behavior of async reset value with preset?

[nandor]

The preset assignment precedes the async reset logic, so nothing should change in that case.

[seldridge]

The preset assignment precedes the async reset logic, so nothing should change in that case.

This makes sense to me. Does the reasoning below make sense?

We should separate out several things.

1. Asynchronous reset value.
2. Asynchronous reset value when reset asserted at time zero.
3. Preset value.

In the IR modeling, these should be kept as distinct things. When targeting FPGA flows, there should be an optional optimization pass that moves asynchronous reset initial values to preset values if the preset value is unset or random.

I think the emission should eventually allow composition of all of these to give you either:

reg foo;
// Asynchronous reset emission w/ random preset:
initial begin
  `ifdef RANDOM_REG
  foo = `RANDOM;
  `endif
  `ifndef SYNTHESIS
  if (reset)
    foo = foo_init_expr;
  `endif
end
always @(posedge clock or posedge reset) begin
  if (reset)
    foo = foo_init_expr;
  else
    /* ... */
end

reg foo;
// Asynchronous reset emission w/ constant preset:
initial begin
  foo = foo_preset_literal;
  `ifndef SYNTHESIS
  if (reset)
    foo = foo_init_expr;
  `endif
end
always @(posedge clock or posedge reset) begin
  if (reset)
    foo = foo_init_expr;
  else
    /* ... */
end

[nandor]

I agree, preset is orthogonal to async reset. On FPGAs we turn async resets to sync resets so we don't have to reason about that crazyness. Unless I am mistaken, now we get what you wrote down, with the exception that we always have a preset, random or constant.

[seldridge]

Alternatively, why not just emit both? The random is ifdef guarded and the preset follows the randomization and is not ifdef guarded.

This logic for emission should already work for this below.

[nandor]

I want these two to be orthogonal. If a register is preset, we don't reset it. I don't want to have to rely on macros here or SV assigment order and madness.

[seldridge]

You've convinced me. 😉 Emitting both is just going to be a useless procedural assignment.