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[FIRRTL] Expose clock dividers as a FIRRTL intrinsic #6890

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merged 1 commit into from Apr 2, 2024
Merged

[FIRRTL] Expose clock dividers as a FIRRTL intrinsic #6890

merged 1 commit into from Apr 2, 2024

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nandor
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@nandor nandor commented Apr 2, 2024

This PR adds an intrinsic to expose seq.clock_div to FIRRTL.

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[FIRRTL] Expose clock dividers as a FIRRTL intrinsic
386a8b3 
This PR adds an intrinsic to expose `seq.clock_div` to FIRRTL.
dtzSiFive
dtzSiFive approved these changes Apr 2, 2024
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LGTM!

Small comment about the wires being inserted here, since they're only done for two intrinsics and because I'm mid re-working how a bunch of this works but nothing blocking 👍 .

lib/Dialect/FIRRTL/Transforms/LowerIntrinsics.cpp Show resolved Hide resolved
@nandor nandor merged commit d84cf8c into main Apr 2, 2024
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@nandor nandor deleted the dev/nandor/clock-div-intrin branch April 2, 2024 15:00
cepheus69 pushed a commit to cepheus69/circt that referenced this pull request Apr 22, 2024
@nandor @cepheus69
[FIRRTL] Expose clock dividers as a FIRRTL intrinsic (llvm#6890)
766ba72 
This PR adds an intrinsic to expose `seq.clock_div` to FIRRTL.
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@dtzSiFive dtzSiFive dtzSiFive approved these changes

@fabianschuiki fabianschuiki Awaiting requested review from fabianschuiki

@darthscsi darthscsi Awaiting requested review from darthscsi darthscsi is a code owner

@seldridge seldridge Awaiting requested review from seldridge seldridge is a code owner

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@nandor @dtzSiFive