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[TargetInstrInfo] update INLINEASM memoperands once #74135

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merged 2 commits into from Dec 4, 2023

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nickdesaulniers
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In commit b053359 ("[X86InstrInfo] support memfold on spillable inline asm
(#70832)"), I had a last minute fix to update the memoperands. I originally
did this in the parent foldInlineAsmMemOperand call, updated the mir test via
update_mir_test_checks.py, but then decided to move it to the child call of
foldInlineAsmMemOperand.

But I forgot to rerun update_mir_test_checks.py. That last minute change caused
the same memoperand to be added twice when recursion occurred (for tied
operands). I happened to get lucky that trailing content omitted from the
CHECK line doesn't result in test failure.

But rerunning update_mir_test_checks.py on the mir test added in that commit
produces updated output. This is resulting in updates to the test that:

  1. conflate additions to the test in child commits with simply updating the
    test as it should have been when first committed.

  2. look wrong because the same memoperand is specified twice (we don't
    deduplicate memoperands when added). Example:

    INLINEASM ... :: (load (s32) from %stack.0) (load (s32) from %stack.0)

Fix the bug, so that in child commits, we don't have additional unrelated test
changes (which would be wrong anyways) from simply running
update_mir_test_checks.py.

Link: #20571

In commit b053359 ("[X86InstrInfo] support memfold on spillable inline asm
(llvm#70832)"), I had a last minute fix to update the memoperands.  I originally
did this in the parent foldInlineAsmMemOperand call, updated the mir test via
update_mir_test_checks.py, but then decided to move it to the child call of
foldInlineAsmMemOperand.

But I forgot to rerun update_mir_test_checks.py. That last minute change caused
the same memoperand to be added twice when recursion occurred (for tied
operands). I happened to get lucky that trailing content omitted from the
CHECK line doesn't result in test failure.

But rerunning update_mir_test_checks.py on the mir test added in that commit
produces updated output. This is resulting in updates to the test that:
1. conflate additions to the test in child commits with simply updating the
   test as it should have been when first committed.
2. look wrong because the same memoperand is specified twice (we don't
   deduplicate memoperands when added). Example:

    INLINEASM ... :: (load (s32) from %stack.0) (load (s32) from %stack.0)

Fix the bug, so that in child commits, we don't have additional unrelated test
changes (which would be wrong anyways) from simply running
update_mir_test_checks.py.

Link: llvm#20571
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github-actions bot commented Dec 1, 2023

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:
git-clang-format --diff 9553e156cb840ba4bc040bbfc1f44dc284a97c86 ae650b4ba46be01cb3f60af371ae16b4baa4d599 -- llvm/lib/CodeGen/TargetInstrInfo.cpp
View the diff from clang-format here.
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 61f5ec668a..c328c79080 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1378,10 +1378,9 @@ bool TargetInstrInfo::getMemOperandWithOffset(
 //  SelectionDAG latency interface.
 //===----------------------------------------------------------------------===//
 
-int
-TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
-                                   SDNode *DefNode, unsigned DefIdx,
-                                   SDNode *UseNode, unsigned UseIdx) const {
+int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
+                                       SDNode *DefNode, unsigned DefIdx,
+                                       SDNode *UseNode, unsigned UseIdx) const {
   if (!ItinData || ItinData->isEmpty())
     return -1;
 

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LGTM.

@nickdesaulniers nickdesaulniers merged commit ec000a6 into llvm:main Dec 4, 2023
1 of 3 checks passed
@nickdesaulniers nickdesaulniers deleted the fixmemrefs branch December 4, 2023 16:15
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2 participants