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[dv] Add riscv_ram_intg_test #2184

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[dv] Add riscv_ram_intg_test #2184

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Commits on Jul 2, 2024

  1. [dv] Add riscv_ram_intg_test 

    This test injects a fault into different MuBi encoded signals within
the prim_ram_1p_scr and prim_ram_1p_adv and checks whether a fatal
alert is triggered.

I have excluded the addr_match signal from FI as its encoding
is not directly checked. If the signal was a MuBi True, a
fault into it is treated by the mubi4_and_hi as a False.
If the signal was a MuBi False, a fault into it is treated
by the mubi4_and_hi also as a False. Hence, no address
collision occurs and the holding register is not returned.

This PR is based on lowRISC#2182 and closes lowRISC#2173.

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
    @nasahlpa
    nasahlpa committed Jul 2, 2024
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