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[fpga] Increase CW310 base clock frequency to 24 MHz #19479

Merged
merged 3 commits into from
Sep 1, 2023
Merged

[fpga] Increase CW310 base clock frequency to 24 MHz #19479

merged 3 commits into from
Sep 1, 2023

Commits on Aug 31, 2023

  1. [test] Ensure keymgr_sideload_otbn_test has enough entropy 

    Put entropy_src into auto mode so the test doesn't run out.

Signed-off-by: Alexander Williams <awill@opentitan.org>
    @a-will @timothytrippel
    a-will authored and timothytrippel committed Aug 31, 2023
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  2. [fpga] Increase CW310 base clock frequency to 24 MHz 

    Set clock frequencies for CW310 to the following

clk_main:    24 MHz
clk_io_div4: 6 MHz

Also improve the SPI_HOST timing constraints to have the correct max
frequency, in addition to multicycle paths reflecting the correct
capture edges.

Lastly, re-sign pre-signed ROM e2e tests as these were updated.

Co-authored-by: Tim Trippel <ttrippel@google.com>
Signed-off-by: Alexander Williams <awill@opentitan.org>
    @a-will @timothytrippel
    a-will and timothytrippel committed Aug 31, 2023
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  3. [test] Fix lack of entropy for wycheproof test 

    The test did not initialize the entropy complex to auto mode, and it
would exhaust the available, finite entropy generated during boot,
leading to freezing and timeouts.

Add this test back to the FPGA suite.

Signed-off-by: Alexander Williams <awill@opentitan.org>
    @a-will @timothytrippel
    a-will authored and timothytrippel committed Aug 31, 2023
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