[fpga] Increase CW310 base clock frequency to 24 MHz #19479
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a-will
requested review from
moidx,
cfrantz,
msfschaffner and
a team
and removed request for
a team
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We probably should consider a separate bucket for cached images for earlgrey_es, though (with a different expiration policy). |
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Or... if not a different expiration policy for the bucket, maybe a release tag with artifacts uploaded to GitHub. |
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We are planning to use gs://hotel-california for design archival process. We are still pending uploading the |
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So this isn't going to work with the presigned ROM images from before the frequency change. What shall we do? Do those tests still provide value on the FPGA? |
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I can pull down these changes, regen the images and resign them, and re-push them if you want? |
That also works. I'll leave it up to you whether you would prefer that over removing the test for CW310 (for example). :) |
This is in accordance with an upstream change [1]. While the register set and other chip attributes are frozen for EarlGrey, the clock frequencies are not. This change will also be backported to the lowRISC/opentitan `earlgrey_es` branch [2]. [1]: lowRISC/opentitan#19368 [2]: lowRISC/opentitan#19479
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I pulled this down and signed the images (I added a single commit with the signed images to make sure they pass CI before squashing), and tried to force push update this branch with 
Which is odd because it does seem to exist, perhaps I don't have permissions to update it? |
Put entropy_src into auto mode so the test doesn't run out. Signed-off-by: Alexander Williams <awill@opentitan.org>
timothytrippel
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I was able to update the branch now, it was a configuration error on my side, my apologies. Let's see if this passes CI, then I can squash the last commit. |
Set clock frequencies for CW310 to the following clk_main: 24 MHz clk_io_div4: 6 MHz Also improve the SPI_HOST timing constraints to have the correct max frequency, in addition to multicycle paths reflecting the correct capture edges. Lastly, re-sign pre-signed ROM e2e tests as these were updated. Co-authored-by: Tim Trippel <ttrippel@google.com> Signed-off-by: Alexander Williams <awill@opentitan.org>
The test did not initialize the entropy complex to auto mode, and it would exhaust the available, finite entropy generated during boot, leading to freezing and timeouts. Add this test back to the FPGA suite. Signed-off-by: Alexander Williams <awill@opentitan.org>
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Since CI passed, I squashed my signing commit to the one that updates the binaries, to maintain the invariant that each commit builds cleanly. This should be read to merge once CI passes again. |
timothytrippel
added
the
Status:Ready to merge
Cherry-pick of #19368 and #19397
This should bring back binary compatibility between the earlgrey_es and master branches for cached FPGA images.