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[fpga] Add timestamp for bitstream identification via USR_ACCESS reg #5279

Merged
merged 1 commit into from
Feb 19, 2021
Merged

[fpga] Add timestamp for bitstream identification via USR_ACCESS reg #5279

merged 1 commit into from
Feb 19, 2021

Commits on Feb 18, 2021

  1. [fpga] Add timestamp for bitstream identification via USR_ACCESS reg 

    This commit modifies the bitstream generation to add a timestamp
in the USR_ACCESS register for later identification. This is useful to
find out which bitstream is currently loaded on a running FPGA.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
    @vogelpi
    vogelpi committed Feb 18, 2021
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