[fpga] Add timestamp for bitstream identification via USR_ACCESS reg #5279
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This commit modifies the bitstream generation to add a timestamp in the USR_ACCESS register for later identification. This is useful to find out which bitstream is currently loaded on a running FPGA. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
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@alphan I successfully tested that the hook works and the setting gets the right value. However, I didn't test that the register can actually be read with the ChipWhisperer API. Since you've been playing around with that, it would be great if you could try it out. |
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Thanks @vogelpi, I'll let you know when I have a chance to try this change. |
imphil
approved these changes
Feb 18, 2021
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Okay, thanks @imphil for the approval. I am merging this then. I don't expect a problem with the CW API, but if we find something it won't be a problem to alter this. |
This was referenced Feb 24, 2021
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This PR modifies the bitstream generation to add a timestamp in the USR_ACCESS register for later identification. This is useful to find out which bitstream is currently loaded on a running FPGA.
We would primarily use this feature for the SCA setup but it doesn't hurt to enable it also for non-SCA targets. This is related to lowRISC/ot-sca#39.