Re-align with OpenTitan

[vogelpi]

Note: This PR needs #41 and #42 to go in first. In addition, it supersedes #40.

This PR re-aligns the binaries and configuration with OpenTitan (commit 1b00157). The relevant changes are:

• Increase spiflash frame size, adjust wait times accordingly. This resolves React to changes in spi and spiflash #34.
• Update aes_serial binary and relevant paths in OpenTitan.
• Update FPGA bitstream (by default OpenTitan now uses domain-oriented masking, short DOM).
• Increase ADC gain and adjust number of samples for DOM.
• Update the sample traces figure as the AES traces look pretty different when using DOM compared to Canright masking or unmasked implementations.

[vogelpi]

FYI @vrozic.

[vogelpi]

Update, #41 and #42 got merged, I've rebased this PR on top of master.

[alphan]

Thanks @vogelpi! Can you apply the following to keep things in sync:

diff --git a/cw/cw305/waverunner.py b/cw/cw305/waverunner.py
index 784927e..961beeb 100644
--- a/cw/cw305/waverunner.py
+++ b/cw/cw305/waverunner.py
@@ -69,7 +69,7 @@ class WaveRunner:
         """
         self._ip_addr = ip_addr
         self.seq_num_waves = 1000
-        self._num_samples = 180
+        self._num_samples = 740
         self._instr = vxi11.Instrument(self._ip_addr)
         self._populate_device_info()
         self._print_device_info()
@@ -134,8 +134,8 @@ class WaveRunner:
         commands = [
             # DC coupling, 1 Mohm.
             "C3:CPL D1M",
-            "C3:VDIV 40MV",
-            "C3:OFST 140MV",
+            "C3:VDIV 35MV",
+            "C3:OFST 105MV",
         ]
         self._write(";".join(commands))
         self._write("vbs 'app.Acquisition.C3.BandwidthLimit = \"200MHz\"'")
@@ -168,12 +168,12 @@ class WaveRunner:
 
     def _configure_timebase(self):
         commands = [
-            "TDIV 200NS",
+            "TDIV 800NS",
             # Trigger delay: Trigger is centered by default. Move to the left to
             # include the samples that we are interested in.
             # Note: This number is tuned to align WaveRunner traces with ChipWhisperer
             # traces.
-            "TRDL -960NS",
+            "TRDL -4950NS",
         ]
         self._write(";".join(commands))
 
@@ -189,7 +189,7 @@ class WaveRunner:
             # NP: number of points, self._num_samples.
             # FP: first point (without decimation).
             # SN: All sequences: 0
-            f"WFSU SP,10,NP,{self._num_samples},FP,0,SN,0",
+            f"WFSU SP,10,NP,{self._num_samples},FP,10,SN,0",
             # Data format: with DEF9 header, bytes (8-bit signed integers), binary encoding.
             # TODO: byte vs. word.
             "CFMT DEF9,BYTE,BIN",

Also, was this bitstream generated after lowRISC/opentitan#5279?

[vogelpi]

Thanks @alphan for having a look. I've updated waverunner.py accordingly (+ made it executable like the other scripts).

Yes, the bitstream does include the identification via USR_ACCESS register.

[alphan]

Thanks @vogelpi! I tried fpga.get_fpga_buildtime() with the new bitstream but it still doesn't return the correct value. I reopened newaetech/chipwhisperer#306 to ask NewAE if there was anything else that needs to be done to enable this. We can debug further after hearing from them.

[vogelpi]

Thanks @alphan for approving the PR and for trying out the buildtime feature. I updated and tested the bitstream and binaries once more just to be sure. I can confirm that the current bitstream has the following timestamp embedded (from the Vivado log):

Overwriting "TIMESTAMP" with "C92B0B41" for option USR_ACCESS
TIMESTAMP = Thu Feb 25 16:45:01 2021

I am now going ahead and merge this to unblock other tasks.