PMP entries before (including) the matched PMP entry may only cover partial
of the TLB page, and this may split the page into regions with different
permissions. Such as for PMP0 (0x80000008~0x8000000F, R) and PMP1 (0x80000000~
0x80000FFF, RWX), write access to 0x80000000 will match PMP1. However we cannot
cache the translation result in the TLB since this will make the write access
to 0x80000008 bypass the check of PMP0. So we should check all of them instead
of the matched PMP entry in pmp_get_tlb_size() and set the tlb_size to 1 in
this case.
Set tlb_size to TARGET_PAGE_SIZE if PMP is not support or there is no PMP rules.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

(cherry picked from commit dc7b599
https://github.com/alistair23/qemu.git riscv-to-apply.next)

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

when `--without-default-features` is used and `--enable-cocoa` is not,
configure script fails as meson does not search for objc compiler but
later attempts to report objc information.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

There are two dscratch registers in current specifications (0.13.2 and 1.0.0)

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

…ion.

From RISC-V Privileged Architecture,

3.1.9. Machine Interrupt Registers (mip and mie)

"Bits 15:0 are allocated to standard interrupt causes only, while bits
16 and above are designated for platform or custom use."

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

semihosting should only be handled as an exception, not as an interrupt

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

from riscv-privileged / 3.1.7 MTVEC Base-Address Register:

"The mtvec register must always be implemented, but can contain a read-only value."

i.e. there should be a way to configure mtvec w/o relying on a CSR write instruction.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Warning: this change impacts all hpmcounters: mcycle, minstret, ...

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Fix issue when enabling an already pending interrupt: the interrupt would not be
triggered properly.

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Fix several issues with ePMP checks on writes to pmpaddr/pmpcfg.

For pmpaddr: Rule Locking Bypass (mseccfg.RLB) was not implemented for writes
to locked entries/rules.

For pmpcfg: with Machine Mode Lockdown (mseccfg.MML) set (and RLB not set),
writes to pmpcfg would be allowed for the wrong cases of ePMP truth table.
The existing code restricts writes like so:
- L=1, X=1: cases 8, 10, 12, 14
- L=0, RWX!=WX: cases 0-2, 4-6
From the ePMP specification: "Adding a rule with executable privileges that
either is M-mode-only or a locked Shared-Region is not possible (...)"
This description matches cases 9-11, 13 of the truth table. This commit
implements the check by using pmp_get_epmp_operation to convert between PMP
configuration and ePMP truth table cases.

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Although Zbr extension once part of bitmanip specification up to v0.94
as not been ratified and even entirely removed from the final v1.0
specification, it is nevertheless used by the lowrisc-ibex core as an
optional ISA, which is enabled in the OpenTitan project.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Follow vendor-device syntax used with other RISCV cores

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Define a generic version of lowrisc-ibex core that can be used in several machines:

 - leave MISA empty so that generic properties can be defined for this core
 - remove all arbitrary default properties but ISA I,C,U which are mandatory for ibex
 - define default mtvec which is only support vectored mode
 - update privilege version (1.12) according to the Ibex documentation
 - define ibex architecture identifier

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

 - remove hart array (mostly useless, its definition is incoherent and
   prevent from applying properties to CPU cores)
 - remove kernel filename option, as it doubles up with firmware option

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Use a separate Kconfig symbol for Ibex UART device:
having an Ibex CPU does not imply usage of this UART implementation.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Use a separate Kconfig symbol for Ibex Timer device:
having an Ibex CPU does not imply usage of this Timer implementation.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Use a separate Kconfig symbol for Ibex SPI Host device:
having an Ibex CPU does not imply usage of this SPI Host implementation.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Legacy OpenTitan machine devices are no longer compatible with current OpenTitan HW.
opentitan machine name is too generic, ot-earlgrey implements the standalone
version for OpenTitan based on CW310 FPGA hardware description.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

As the static function is a callback, it should be considered as a public
function whose arguments should be sanity-checked.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

(for debug only)

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Add two functions:
- fifo8_peek_buf: same as fifo8_pop_buf but does not consume data from the
  FIFO
- fifo8_consume_all: only consume data bytes from the FIFO

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

…mentation

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

This script extract io_read/write information from a QEMU log script and
compare the device register values against the HW reset values and
guest SW modified ones.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Add property no_pmp_cfg on EarlGrey machine to disable default ePMP
configuration.

Usage:
  qemu-system-riscv32 -M ot-earlgrey,no-epmp-cfg=true [...]

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

pre-existing 32-bit FIFO implementation uses a 8-bit backend

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

This basic device only supports RND registers for now.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>