ADS8686 channel 'A', 'B' not synchronized

[lucask07]

The ADS8686 channel 'A', 'B' are stored into the DDR at different 'cycle_cnts'. This was causing slight errors in impedance analyzer measurements until I shifted the channel 'A' results one cycle.

Instead in the FPGA code, we should store 'A', 'B' results at the same cycle count so that there is no need to synchronize in software. (Unfortunately, this will require edits to the function to read .h5 files data_to_names and will make old .h5 files incompatible with newer .h5 files).

[lucask07]

This is addressed and tested (fixed impedance analyzer issues) in the ads_sync branch.