Bring Circuit to 100% correctness

[porcuquine]

This is a tracking issue which should not be closed until all known circuit issues have been resolved.

Known issues:

• (fib 100) proofs fail to verify. [verified fixed in Only synthesize one circuit_frame at a time in Nova tests. #113]
• test_create_open_and_verify_complicated_higher_order_functional_commitment2 fails (fcomm).
• Error handling: in some cases either eval or circuit synthesis panics in error cases. Both should return explicit error.
• FIXME: There are some cases in the circuit marked with FIXME because some known implementation detail has been deferred.

[porcuquine]

@emmorais Can you confirm that the last two boxes here can be checked? I also just tested the second and found it to pass after uncommenting. It would be valuable to get independent confirmation of that also.

[huitseeker]

@porcuquine @emmorais Can this be closed?

[emmorais]

Yes, all FIXES where either fixed or an issue were created; bugs were fixed; and error handling was implemented. In my opinion it can be closed. @porcuquine, do you see anything still missing here?

[huitseeker]

@porcuquine Feel free to reopen if you think something is missing. 100% of the audit correctness items are fixed.