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Welcome to the fpga-tidbits wiki! This is where the project documentation for fpga-tidbits will be gradually appearing.

What is this anyway? fpga-tidbits is a library of hardware components (or more accurately, hardware component generators) written in Chisel. It is primarily intended for FPGA projects, though most of the generated Verilog should be usable for other hardware designs as well.

How do I use it in my projects? If you have a Chisel project, just add the fpga-tidbits to your source directory (either under src/main/scala or similar to this), import the desired package(s) and you're set. You could, of course, also use the Chisel-generated Verilog as part of a larger VHDL/Verilog project.

What functionality is available? Currently, the following wiki pages describing the per-folder functionality are available:

• dma - for accessing external memory interfaces
• interfaces - several interface definitions (AXI MM, Convey)
• math - pipelined, streaming math operators
• onchipmemory - FPGA dual-port BRAM and queues (BRAM and SRL-based)
• platformwrapper - for making cross-platform FPGA accelerators
• profiler - for state monitoring/profiling
• regfile - register file with external read/write interface
• streams - for working with streams, Decoupled (ready-valid) interfaces

How can I help? See the TODOs page.