TODOs

General

• write unit tests (JUnit + Chisel.Tester) for all components
• write documentation
• add synthesis result examples, similar to Christopher Felton's alt.hdl

DMA

• support write bursts (will need stateful interleavers, also stateful simplex adapters for Convey)
• get rid of dedicated reinitialize signal for ReqIDQueue, use regular reset

PlatformWrapper

• tighter packing of fields into registers (right now, 1-bit signal will occupy 32-bit register)
• allow placing constraints on I/O ports in hardware description & gen check in SW driver (e.g divisable by x)
• add illegal memory access exceptions in TesterWrapper (unaligned access, unsupported burst size, invalid address)
• add support for the Zynq ACP ports
• add OoO returns support in high-latency memory simulation

Streams

• make a handshaking-across-latency wrapper component