I've succesfully dumped the boot ROM of my SPARCstation ELC and added
preliminary support for it to MAME based on the existing Sun4 work.

This patch manages to get the ELC emulation to get to the Open Firmware
prompt, but booting any OS media (eg Solaris/SunOS/NetBSD) results in an
illegal instruction error on the OF prompt.

The emulation passes the boot diagnostics:

m_cache_tag_shift 3
m_page_mask 000003ff
m_seg_entry_shift 0000000a
m_seg_entry_mask 0000003f
m_page_entry_mask 0000ffff
m_cache_mask 00003fff

EPROM Checksum Test
Power-Up State Test
Context Register Bit Test
Context Register Addressing Test
Segment Map RAM MATS Pattern Test, Context 00000000
Segment Map RAM MATS Pattern Test, Context 00000001
Segment Map RAM MATS Pattern Test, Context 00000002
Segment Map RAM MATS Pattern Test, Context 00000003
Segment Map RAM MATS Pattern Test, Context 00000004
Segment Map RAM MATS Pattern Test, Context 00000005
Segment Map RAM MATS Pattern Test, Context 00000006
Segment Map RAM MATS Pattern Test, Context 00000007
Page Map RAM MATS Pattern Test
Limit 0 Register Test
Counter Interrupt Level 10 Test
Limit 1 Register Test
Counter Interrupt Level 14 Test
Synchronous Error Reg Test
Synchronous Error Virtual Address Reg Test
Asynchronous Error Reg Test
Asynchronous Error Virtual Address Reg Test
Asynchronous Error Data Reg1 Test
Asynchronous Error Data Reg2 Test
System Enable Register Bit Test
Cache Data RAM MATS Pattern Test
Cache Tag RAM MATS Pattern Test
PTE Access Bit Test
PTE Modify Bit Test
PTE Write-Protect Bit Test
PTE Write-Invalid Bit Test
PTE Read-Invalid Bit Test
PTE Type 2 Space Bit Test
PTE Type 3 Space Bit Test
Synchronous Timeout Test
Asynchronous Timeout Test
**** 16 MegaBytes Found in Address Range 0x00000000 to 0x00ffffff ****
**** 16 MegaBytes Found in Address Range 0x01000000 to 0x01ffffff ****
**** 16 MegaBytes Found in Address Range 0x02000000 to 0x02ffffff ****
**** 16 MegaBytes Found in Address Range 0x03000000 to 0x03ffffff ****
DRAM Word MATS Pattern Test (0x00fe0000 - 0x01000000)
Parity/Memory Control Registers Bit Test
36-bit SIMM Parity Test
33-bit SIMM Parity Test
Interrupt Register Test
Software Interrupt Level 1 Test
Software Interrupt Level 4 Test
Software Interrupt Level 6 Test
NVRAM Access Test
TOD Clock Oscillator Running
TOD Registers Test
Cache Statistics Bit Update Test
Cache Doubleword-Alignment Read Miss Test
Cache TAG Comparator Read Miss Test
Cache Non-Cacheable Read Miss Test
Cache Read Miss Parity Test
Cache Doubleword-Alignment Read Hit Test
Cache Byte-Alignment Read Hit Test
Cache Read Hit Context Test
Cache Read Hit MMU Invalid Test
Cache Doubleword-Alignment Write Hit Test
Cache TAG Comparator Write Hit Test
Cache Write Hit Context Test
Cache Write Hit/Miss (Cacheable) Test
Cache Write Hit/Miss (Non-Cacheable) Test
Cache Write Miss Test
Software Context Flush Test
Software Segment Flush Test
Software Page Flush Test
Hardware Context Flush Test
Hardware Segment Flush Test
Hardware Page Flush Test
Unconditional Block Flush Test
FPU Misaligned Register Pair Test
FPU Single-Precision Test
Single-Precision FPU Exception (Invalid Result) Test
Single-Precision FPU Exception (Overflow) Test
Single-Precision FPU Exception (Underflow) Test
Single-Precision FPU Exception (Divide-by-0) Test
Single-Precision FPU Exception (Inexact Result) Test
Single-Precision FPU Exception and Timeout Test
Single-Precision FPU Exception and Data-Access Trap Test
Single-Precision FPU Exception and Misalignment Test
Single-Precision FPU Exception and Asynchronous Trap Test
FPU Double-Precision Test
Double-Precision FPU Exception (Invalid Result) Test
Double-Precision FPU Exception (Overflow) Test
Double-Precision FPU Exception (Underflow) Test
Double-Precision FPU Exception (Divide-by-0) Test
Double-Precision FPU Exception (Inexact Result) Test
Double-Precision FPU Exception and Timeout Test
Double-Precision FPU Exception and Data-Access Trap Test
Double-Precision FPU Exception and Misalignment Test
Double-Precision FPU Exception and Asynchronous Trap Test
Setting Segment Map
Setting RAM Parity Mode
 Mode set to 36-bit
Sizing Memory
Mapping ROM
Mapping RAM
Can't find keyboard table for keyboard layout code 21
Using USA keyboard table
Probing /sbus@1,f8000000 at 0,0  dma esp sd st le
Probing /sbus@1,f8000000 at 1,0  Nothing there
Probing /sbus@1,f8000000 at 2,0  Nothing there
Probing /sbus@1,f8000000 at 3,0  bwtwo

I had to make this local change to support current MSVC breaking the
build. Removed it to separate it from the sun4/25 support PR.

Update indentation as requested by @cuavas during the PR review.