Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Output Multiplexer #2

Closed
4 tasks done
Tracked by #6
martinhofigueiredo opened this issue Apr 19, 2023 · 0 comments
Closed
4 tasks done
Tracked by #6

Output Multiplexer #2

martinhofigueiredo opened this issue Apr 19, 2023 · 0 comments
Assignees
Milestone

Comments

@martinhofigueiredo
Copy link
Owner

martinhofigueiredo commented Apr 19, 2023

To Do:

  • Domino Logic Implementation
  • Transmission Gates Implementation
  • Sizing
  • Test

The output multiplexer is 4:1 meaning we need 2 bit to encode all possible

S is a bus S<0:1>

image
Transmission Gate implementation

@martinhofigueiredo martinhofigueiredo self-assigned this Apr 19, 2023
@martinhofigueiredo martinhofigueiredo added this to the 1B ALU milestone Apr 19, 2023
@martinhofigueiredo martinhofigueiredo mentioned this issue Apr 23, 2023
5 tasks
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant