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Original repository at: git://git.bues.ch/crcgen.git
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mbuesch main: Remove unnecessary call to main()
Signed-off-by: Michael Buesch <m@bues.ch>
Latest commit 1e81181 Aug 14, 2019
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crcgen main: Remove unnecessary call to main() Aug 14, 2019
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scripts main: Remove unnecessary call to main() Aug 14, 2019
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COPYING Initial commit Jul 30, 2019
MANIFEST.in Add build framework Aug 13, 2019
README.rst Add build framework Aug 13, 2019
crcgen_test.py test: Add 64bit coefficients Aug 13, 2019
setup.py Add crcgen main script Aug 13, 2019

README.rst

CRC algorithm code generator

This tool generates synthesizable Verilog code for use in FPGAs to calculate CRC (Cyclic Redundancy Check) checksums.

License

Copyright (c) 2019 Michael Buesch <m@bues.ch>

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

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