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  • University of California, Santa Barbara
  • Santa Barbara
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Pinned

  1. jasonlin316/RISC-V-CPU jasonlin316/RISC-V-CPU Public

    A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

    Verilog 95 21

  2. 108-1-Computer-Architecture 108-1-Computer-Architecture Public

    NTUEE Computer Architecture, Fall 2019

    Verilog

  3. 108-2-Digital-System-Design 108-2-Digital-System-Design Public

    NTUEE Digital System Design, Spring 2020

    Verilog

  4. ECE272A-Machine-Learning-in-Design-and-Test-Automation ECE272A-Machine-Learning-in-Design-and-Test-Automation Public

    UCSB ECE272A instructed by Prof. Li-C. Wang in Fall 2021

    Python

  5. Judge-Girl-Problem-Set Judge-Girl-Problem-Set Public

    https://judgegirl.csie.org/#

    C

  6. ECE253-Embedded-Systems-Design ECE253-Embedded-Systems-Design Public

    UCSB ECE253 Embedded Systems Design instructed by Prof. Forrest Brewer in Fall 2021

    C 1