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University of California, Santa Barbara
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jasonlin316/RISC-V-CPU
jasonlin316/RISC-V-CPU PublicA RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
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108-1-Computer-Architecture
108-1-Computer-Architecture PublicNTUEE Computer Architecture, Fall 2019
Verilog
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108-2-Digital-System-Design
108-2-Digital-System-Design PublicNTUEE Digital System Design, Spring 2020
Verilog
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ECE272A-Machine-Learning-in-Design-and-Test-Automation
ECE272A-Machine-Learning-in-Design-and-Test-Automation PublicUCSB ECE272A instructed by Prof. Li-C. Wang in Fall 2021
Python
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ECE253-Embedded-Systems-Design
ECE253-Embedded-Systems-Design PublicUCSB ECE253 Embedded Systems Design instructed by Prof. Forrest Brewer in Fall 2021
C 1
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