RaspberryPi2/3 UEFI source code as of Windows10 RS1 release

ms-iot · Oct 22, 2016 · 42edc35 · 42edc35
1 parent b81715b
commit 42edc35
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diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/Arm/ArmCortexA5xHelper.S b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/Arm/ArmCortexA5xHelper.S
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
+# Copyright (c) Microsoft Corporation. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroIoLib.h>
+
+.text
+.align 3
+GCC_ASM_EXPORT (ArmReadCpuExCr)
+GCC_ASM_EXPORT (ArmWriteCpuExCr)
+
+ASM_PFX(ArmReadCpuExCr):
+  mrrc    p15, 1, r0, r1, c15
+  bx      lr
+
+ASM_PFX(ArmWriteCpuExCr):
+  mcrr    p15, 1, r0, r1, c15
+  dsb
+  isb
+  bx      lr
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/Arm/ArmCortexA5xHelper.asm b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/Arm/ArmCortexA5xHelper.asm
@@ -0,0 +1,36 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
+// Copyright (c) Microsoft Corporation. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+#include <AsmMacroIoLib.h>
+
+    INCLUDE AsmMacroIoLib.inc
+
+    EXPORT ArmReadCpuExCr
+    EXPORT ArmWriteCpuExCr
+
+    AREA ArmCortexA5xHelper, CODE, READONLY
+
+ArmReadCpuExCr
+  mrrc    p15, 1, r0, r1, c15
+  bx      lr
+
+ArmWriteCpuExCr
+  mcrr    p15, 1, r0, r1, c15
+  dsb
+  isb
+  bx      lr
+
+
+  END
diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
@@ -1,6 +1,7 @@
 /** @file
 
   Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+  Copyright (c) Microsoft Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -27,26 +28,33 @@ ArmCpuSetup (
   )
 {
   // Check if Architectural Timer frequency is valid number (should not be 0)
-  ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
+  ASSERT (FixedPcdGet32 (PcdArmArchTimerFreqInHz));
   ASSERT (ArmIsArchTimerImplemented () != 0);
 
   // Note: System Counter frequency can only be set in Secure privileged mode,
   // if security extensions are implemented.
-  ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
+  ArmGenericTimerSetTimerFreq (FixedPcdGet32 (PcdArmArchTimerFreqInHz));
 
   if (ArmIsMpCore ()) {
     // Turn on SMP coherency
     ArmSetCpuExCrBit (A5X_FEATURE_SMP);
   }
 
   //
-  // If CPU is CortexA57 r0p0 apply Errata: 806969
-  //
+  // If CPU is CortexA57 r0p0 apply Errata
+  // TODO: Port the Cortex-A57 errata fix below to AArch32 by implementing
+  // ArmSetCpuActlrBit for AArch32
+  ASSERT ((ArmReadMidr() & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) !=
+    ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0, 0)));
+  /*
   if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
-                         ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
-    // DisableLoadStoreWB
-    ArmSetCpuActlrBit (1ULL << 49);
+                        ((ARM_CPU_TYPE_A57  << 4) | ARM_CPU_REV(0,0))) {
+    // Errata 806969: DisableLoadStoreWB (1ULL << 49) 
+    // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate  (1ULL << 44)
+    // Errata 814670: disable DMB nullification (1ULL << 58)
+    ArmSetCpuActlrBit ((1ULL << 49) | (1ULL << 44) | (1ULL << 58));
   }
+  */
 }
 
 VOID

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
@@ -1,6 +1,6 @@
 #/* @file
 #  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-#
+#  Copyright (c) Microsoft Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
@@ -34,5 +34,9 @@
 [Sources.AARCH64]
   AArch64/ArmCortexA5xHelper.S | GCC
 
+[Sources.ARM]
+  Arm/ArmCortexA5xHelper.S   | GCC
+  Arm/ArmCortexA5xHelper.asm | RVCT
+
 [FixedPcd]
   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
@@ -2,6 +2,7 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) Microsoft Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -24,6 +25,7 @@
 
 // ID_PFR1 - ARM Processor Feature Register 1 definitions
 #define ARM_PFR1_SEC        (0xFUL << 4)
+#define ARM_PFR1_VIRT       (0xFUL << 12)
 #define ARM_PFR1_TIMER      (0xFUL << 16)
 #define ARM_PFR1_GIC        (0xFUL << 28)
 

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
@@ -1,7 +1,8 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) Microsoft Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -424,6 +425,12 @@ ArmSetTTBR0 (
   IN  VOID  *TranslationTableBase
   );
 
+VOID
+EFIAPI
+ArmSetTTBCR (
+  IN  UINT32 Bits
+  );
+
 VOID *
 EFIAPI
 ArmGetTTBR0BaseAddress (
@@ -543,7 +550,6 @@ ArmCallWFE (
 VOID
 EFIAPI
 ArmCallWFI (
-
   VOID
   );
 

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -2,6 +2,7 @@
 *  File managing the MMU for ARMv7 architecture
 *
 *  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*  Copyright (c) Microsoft Corporation. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -279,6 +280,12 @@ ArmConfigureMmu (
 
   ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
 
+  //
+  // Initialize TTBCR to set 32-bit translation system with the Short-descriptor translation table format,
+  // and perform translation table walks using TTBR0
+  //
+  ArmSetTTBCR (0);
+
   ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
                              DOMAIN_ACCESS_CONTROL_NONE(14) |
                              DOMAIN_ACCESS_CONTROL_NONE(13) |

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -1,7 +1,8 @@
 #------------------------------------------------------------------------------
 #
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.<BR>
+# Copyright (c) Microsoft Corporation. All rights reserved.<BR>
 #
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
@@ -29,6 +30,7 @@ GCC_ASM_EXPORT(ArmGetInterruptState)
 GCC_ASM_EXPORT(ArmGetFiqState)
 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
 GCC_ASM_EXPORT(ArmSetTTBR0)
+GCC_ASM_EXPORT(ArmSetTTBCR)
 GCC_ASM_EXPORT(ArmSetDomainAccessControl)
 GCC_ASM_EXPORT(CPSRMaskInsert)
 GCC_ASM_EXPORT(CPSRRead)
@@ -117,6 +119,11 @@ ASM_PFX(ArmSetTTBR0):
   isb
   bx      lr
 
+ASM_PFX(ArmSetTTBCR):
+  mcr     p15,0,r0,c2,c0,2
+  isb
+  bx      lr
+
 ASM_PFX(ArmGetTTBR0BaseAddress):
   mrc     p15,0,r0,c2,c0,0
   LoadConstantToReg(0xFFFFC000, r1)
@@ -153,6 +160,7 @@ ASM_PFX(ArmReadScr):
 
 ASM_PFX(ArmWriteScr):
   mcr     p15, 0, r0, c1, c1, 0
+  isb
   bx      lr
 
 ASM_PFX(ArmReadHVBar):

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
@@ -1,7 +1,8 @@
 //------------------------------------------------------------------------------
 //
 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
+// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.<BR>
+// Copyright (c) Microsoft Corporation. All rights reserved.<BR>
 //
 // This program and the accompanying materials
 // are licensed and made available under the terms and conditions of the BSD License
@@ -29,6 +30,7 @@
     EXPORT ArmGetFiqState
     EXPORT ArmGetTTBR0BaseAddress
     EXPORT ArmSetTTBR0
+    EXPORT ArmSetTTBCR
     EXPORT ArmSetDomainAccessControl
     EXPORT CPSRMaskInsert
     EXPORT CPSRRead
@@ -117,6 +119,11 @@ ArmSetTTBR0
   isb
   bx      lr
 
+ArmSetTTBCR
+  mcr     p15,0,r0,c2,c0,2
+  isb
+  bx      lr
+
 ArmGetTTBR0BaseAddress
   mrc     p15,0,r0,c2,c0,0
   LoadConstantToReg(0xFFFFC000, r1)
@@ -153,6 +160,7 @@ ArmReadScr
 
 ArmWriteScr
   mcr     p15, 0, r0, c1, c1, 0
+  isb
   bx      lr
 
 ArmReadHVBar

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -1,6 +1,7 @@
 #/** @file
 #
 #  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -88,6 +89,12 @@
   # Size to reserve in the primary core stack for SEC Global Variables
   gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031
 
+  # Mailbox base for the Multi-Processor Parking Protocol
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresMPPPMailboxBase|0|UINT32|0x0000003E
+  # Mailbox size (per mailbox/core) for the Multi-Processor Parking Protocol.
+  # The spec requires 4Kb per mailbox.
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresMPPPMailboxSize|0x1000|UINT32|0x0000003F
+
   # Boot Monitor FileSystem
   gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A
 
@@ -122,6 +129,13 @@
   gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
   gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
 
+  ## WOA Entries start at 0x00000040 ##
+  gArmPlatformTokenSpaceGuid.PcdCpuParkedAddress|0x00000000|UINT64|0x00000042
+  gArmPlatformTokenSpaceGuid.PcdParkingMailboxSize|0x00010000|UINT64|0x00000452
+  gArmPlatformTokenSpaceGuid.PcdBootMonCpuMailboxAddress|0|UINT32|0x00000049
+  gArmPlatformTokenSpaceGuid.PcdRestrictCoreCount|0|UINT32|0x0000004A
+  gArmPlatformTokenSpaceGuid.PcdRestrictClusters|0|UINT32|0x0000004B
+
   #
   # BDS - Boot Manager
   #
@@ -143,6 +157,13 @@
 
   gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
   gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootAppPath|L""|VOID*|0x00000040
+  gArmPlatformTokenSpaceGuid.PcdPreBootAppPath|L""|VOID*|0x00000041
+
+  gArmPlatformTokenSpaceGuid.PcdEmbeddedAutomaticBootTimeOut|0xffff|UINT16|0x0000002E
+
+  # Secure boot GUID. Include/Guid/WinSecureBoot.h
+  gArmPlatformTokenSpaceGuid.PcdSecureBootPolicy|{ 0xdb,0xda,0xa0,0x2c,0x3e,0xa1,0x4e,0x21,0xa4,0x54,0x80,0xd4,0x7c,0xa6,0x95,0xcf }|VOID*|0
 
 [PcdsFixedAtBuild.common,PcdsDynamic.common]
   ## PL031 RealTimeClock
@@ -160,4 +181,7 @@
   # and PcdCPUCoreSecSecondaryStackSize
   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
+
+[PcdsDynamic, PcdsDynamicEx]
+  gArmPlatformTokenSpaceGuid.PcdBootOptionSelected|1|UINT32|0x00000444