Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[BUG] Linting with iverilog have a display bug in port list #476

Closed
athgx1994 opened this issue Apr 5, 2024 · 1 comment · Fixed by #501
Closed

[BUG] Linting with iverilog have a display bug in port list #476

athgx1994 opened this issue Apr 5, 2024 · 1 comment · Fixed by #501
Labels

Comments

@athgx1994
Copy link

Describe the bug
Module port list shows a visualization fault on last entry. It will always be displayed in blue instead of white like the other port names (see screenshot!)

Environment (please complete the following information):

  • OS: Windows 10
  • VS Code version 1.88.0
  • Extension version 1.13.5
  • lint tool: icarus iverilog

image

@OmarElfouly
Copy link
Contributor

Hello @mshr-h

I found and fixed the issue :)

Screenshot from 2024-10-24 13-08-13

It was an overmatching pattern in the verilog.tmLanguage.json that I fixed by adding a negative lookahead to the regex so it wont count it as entity.name.tag.module.reference.verilog instead of keyword.other.verilog

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

Successfully merging a pull request may close this issue.

2 participants