[BUG] Linting with iverilog have a display bug in port list

[athgx1994]

Describe the bug
Module port list shows a visualization fault on last entry. It will always be displayed in blue instead of white like the other port names (see screenshot!)

Environment (please complete the following information):

• OS: Windows 10
• VS Code version 1.88.0
• Extension version 1.13.5
• lint tool: icarus iverilog

[OmarElfouly]

Hello @mshr-h

I found and fixed the issue :)

It was an overmatching pattern in the verilog.tmLanguage.json that I fixed by adding a negative lookahead to the regex so it wont count it as entity.name.tag.module.reference.verilog instead of keyword.other.verilog