Attempt to address #98 and related issues

myhdl/conversion/_toVHDL.py

@@ -1103,17 +1103,13 @@ def visit_Expr(self, node):
             self.write(';')
 
     def visit_IfExp(self, node):
-        pre, suf = self.inferCast(node.vhd, node.body.vhdOri)
-        self.write(pre)
+        # propagate the node's vhd attribute  
+        node.body.vhd = node.orelse.vhd = node.vhd
         self.visit(node.body)
-        self.write(suf)
         self.write(' when ')
         self.visit(node.test)
         self.write(' else ')
-        pre, suf = self.inferCast(node.vhd, node.orelse.vhdOri)
-        self.write(pre)
         self.visit(node.orelse)
-        self.write(suf)
 
     def visit_For(self, node):
         self.labelStack.append(node.breakLabel)
@@ -1289,7 +1285,7 @@ def getName(self, node):
             else:
                 s = "True"
         elif n == 'None':
-            if node.vhd.size == 1:
+            if isinstance(node.vhd, vhd_std_logic):
                 s = "'Z'"
             else:
             	s = "(others => 'Z')"

myhdl/test/bugs/test_issue_18.py

@@ -27,5 +27,5 @@ def read():
 
 def test_issue_18():
     toVHDL.std_logic_ports = True
-    analyze(issue_18, dout, din, addr, we, clk) == 0
+    assert analyze(issue_18, dout, din, addr, we, clk) == 0
 

myhdl/test/bugs/test_issue_98.py

@@ -0,0 +1,40 @@
+from myhdl import *
+from myhdl.conversion import analyze
+
+import pytest
+
+def issue_98(sda, scl, sda_i, sda_o, scl_i, scl_o):
+     sda_d, scl_d = sda.driver(), scl.driver()
+     @always_comb
+     def hdl():
+         sda_i.next = sda
+         #sda_d.next = 0 if not sda_o else None 
+         scl_i.next = scl
+         #scl_d.next = None if not scl_o else 1 
+         scl_d.next = None 
+     return hdl
+
+@pytest.mark.xfail(analyze.simulator in ('vcom', 'GHDL'), 
+                   reason="requires VHDL support for ternary operator")
+def test_issue_98_1():
+    sda_i, sda_o, scl_i, scl_o = [Signal(False) for i in range(4)]
+    sda, scl = [TristateSignal(False) for i in range(2)]
+    toVHDL.name = 'issue_98_1'
+    assert analyze(issue_98, sda, scl, sda_i, sda_o, scl_i, scl_o) == 0
+
+@pytest.mark.xfail(analyze.simulator in ('vcom', 'GHDL'), 
+                   reason="requires VHDL support for ternary operator")
+def test_issue_98_2():
+    sda_i, sda_o, scl_i, scl_o = [Signal(intbv(0)[2:0]) for i in range(4)]
+    sda, scl = [TristateSignal(intbv(0)[2:0]) for i in range(2)]
+    toVHDL.name = 'issue_98_2'
+    assert analyze(issue_98, sda, scl, sda_i, sda_o, scl_i, scl_o) == 0
+
+@pytest.mark.xfail(analyze.simulator in ('vcom', 'GHDL'), 
+                   reason="requires VHDL support for ternary operator")
+def test_issue_98_3():
+    sda_i, sda_o, scl_i, scl_o = [Signal(intbv(0)[1:0]) for i in range(4)]
+    sda, scl = [TristateSignal(intbv(0)[1:0]) for i in range(2)]
+    toVHDL.name = 'issue_98_3'
+    assert analyze(issue_98, sda, scl, sda_i, sda_o, scl_i, scl_o) == 0
+