Move to use VHDL 2008's to_string

myhdl/conversion/_analyze.py

@@ -578,10 +578,14 @@ def visit_Call(self, node):
             node.obj = int(0) # XXX
         elif f is bool:
             node.obj = bool()
-        elif f in _flatten(integer_types, ord):
+        elif f in _flatten(integer_types):
             node.obj = int(-1)
 ##         elif f in (posedge , negedge):
 ##             node.obj = _EdgeDetector()
+        elif f is ord:
+            node.obj = int(-1)
+            if not (isinstance(node.args[0], ast.Str) and (len(node.args[0].s) == 1)):
+                self.raiseError(node, _error.NotSupported, "ord: expect string argument with length 1")
         elif f is delay:
             node.obj = delay(0)
         ### suprize: identity comparison on unbound methods doesn't work in python 2.5??
@@ -915,6 +919,8 @@ def visit_Print(self, node):
                         s = s[m.end():]
                         continue
                     self.raiseError(node, _error.UnsupportedFormatString, "%s" % s)
+            elif isinstance(n, ast.Str):
+                f.append(n.s)
             else:
                 f.append(defaultConvSpec)
                 a.append(n)

myhdl/conversion/_toVHDL.py

@@ -602,9 +602,9 @@ def inferCast(self, vhd, ori):
                     pre, suf = "", "(0)"
                 else:
                     pre, suf = "stdl(", ")"
-        elif isinstance(vhd, vhd_string):
-            if isinstance(ori, vhd_enum):
-                pre, suf = "%s'image(" % ori._type._name, ")"
+        # elif isinstance(vhd, vhd_string):
+        #     if isinstance(ori, vhd_enum):
+        #         pre, suf = "%s'image(" % ori._type._name, ")"
 
         return pre, suf
 
@@ -949,11 +949,10 @@ def visit_Call(self, node):
             return
         elif f is ord:
             opening, closing = '', ''
-            if isinstance(node.args[0], ast.Str):
-                if len(node.args[0].s) > 1:
-                    self.raiseError(node, _error.UnsupportedType, "Strings with length > 1" )
-                else:
-                    node.args[0].s = ord(node.args[0].s)
+            v = ord(node.args[0].s)
+            node.args[0].s = v
+            self.write(v)
+            return
         elif f in integer_types:
             opening, closing = '', ''
             pre, suf = self.inferCast(node.vhd, node.vhdOri)
@@ -1357,13 +1356,9 @@ def visit_Print(self, node):
                         a.vhd = vhd_boolean()
                     elif isinstance(a.vhdOri, vhd_enum):
                         a.vhd = vhd_string()
-                self.write("write(L, ")
+                self.write("write(L, to_string(")
                 self.visit(a)
-                if s.justified == 'LEFT':
-                    self.write(", justified=>LEFT")
-                if s.width:
-                    self.write(", field=>%s" % s.width)
-                self.write(")")
+                self.write("))")
                 self.write(';')
             self.writeline()
         self.write("writeline(output, L);")

myhdl/conversion/_toVerilog.py

@@ -151,7 +151,7 @@ def __call__(self, func, *args, **kwargs):
         genlist = _analyzeGens(arglist, h.absnames)
         siglist, memlist = _analyzeSigs(h.hierarchy)
         _annotateTypes(genlist)
-        
+
         intf = _analyzeTopFunc(func, *args, **kwargs)
         intf.name = name
         doc = _makeDoc(inspect.getdoc(func))
@@ -750,11 +750,7 @@ def visit_Call(self, node):
             return
         elif f is ord:
             opening, closing = '', ''
-            if isinstance(node.args[0], ast.Str):
-                if len(node.args[0].s) > 1:
-                    self.raiseError(node, _error.UnsupportedType, "Strings with length > 1")
-                else:
-                    node.args[0].s = str(ord(node.args[0].s))
+            node.args[0].s = str(ord(node.args[0].s))
         elif f in integer_types:
             opening, closing = '', ''
             # convert number argument to integer