Merge pull request #112 from josyb/TristateWarnings

Added Code to remove inappropriate warnings on Tristate Ports and TristateDrivers
myhdl · Jul 20, 2015 · 983a169 · 983a169
2 parents 7a10469 + bdef4c0
commit 983a169
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Showing 2 changed files with 14 additions and 11 deletions.
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
@@ -53,6 +53,7 @@
 from myhdl.conversion._toVHDLPackage import _package
 from myhdl._util import  _flatten
 from myhdl._compat import integer_types, class_types, StringIO
+from myhdl._ShadowSignal import _TristateSignal, _TristateDriver
 
 
 _version = myhdl.__version__.replace('.','')
@@ -325,10 +326,11 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPor
             if convertPort:
                 pt = "std_logic_vector"
             if s._driven:
-                if s._read:
-                    warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
-                                  category=ToVHDLWarning
-                                  )
+                if s._read :
+                    if not isinstance(s, _TristateSignal):
+                        warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
+                                      category=ToVHDLWarning
+                                      )
                     f.write("\n        %s: inout %s%s" % (portname, pt, r))
                 else:
                     f.write("\n        %s: out %s%s" % (portname, pt, r))
@@ -398,7 +400,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
         r = _getRangeString(s)
         p = _getTypeString(s)
         if s._driven:
-            if not s._read:
+            if not s._read and not isinstance(s, _TristateDriver):
                 warnings.warn("%s: %s" % (_error.UnreadSignal, s._name),
                               category=ToVHDLWarning
                               )

diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py
@@ -50,7 +50,7 @@
 from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc,
                                        _Ram, _Rom)
 from myhdl._Signal import _Signal
-
+from myhdl._ShadowSignal import _TristateSignal, _TristateDriver
 
 _converting = 0
 _profileFunc = None
@@ -253,10 +253,11 @@ def _writeModuleHeader(f, intf, doc):
         r = _getRangeString(s)
         p = _getSignString(s)
         if s._driven:
-            if s._read:
-                warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
-                              category=ToVerilogWarning
-                              )
+            if s._read :
+                if not isinstance(s, _TristateSignal):
+                    warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
+                                  category=ToVerilogWarning
+                                  )
             print("output %s%s%s;" % (p, r, portname), file=f)
             if s._driven == 'reg':
                 print("reg %s%s%s;" % (p, r, portname), file=f)
@@ -281,7 +282,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
         r = _getRangeString(s)
         p = _getSignString(s)
         if s._driven:
-            if not s._read:
+            if not s._read and not isinstance(s, _TristateDriver):
                 warnings.warn("%s: %s" % (_error.UnreadSignal, s._name),
                               category=ToVerilogWarning
                               )