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Added gateware/FPGA project as submodule

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9600 committed Jun 7, 2016
1 parent 01e578a commit c1e6d1ce382b3fef73cccd49d0a1d3838b3957d0
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  1. +3 −0 .gitmodules
  2. +1 −0 gateware
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[submodule "gateware"]
path = gateware
url = https://github.com/myriadrf/LimeSDR-PCIe_GW.git
Submodule gateware added at e11ab3

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