Ver.2.17. Merge branch master_fix

output_files/LimeSDR-USB_lms7_trx_HW_1.4.map

@@ -10,7 +10,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 Notes:
 
-- Data checksum for this conversion is 0x0F44D5B1
+- Data checksum for this conversion is 0x0F282FA6
 
 - All the addresses in this file are byte addresses
 

src/rx_path_top/data2packets/synth/data2packets_top.vhd

@@ -34,7 +34,8 @@ entity data2packets_top is
       pct_buff_wrdata   : out std_logic_vector(63 downto 0);
       smpl_buff_rdusedw : in std_logic_vector(smpl_buff_rdusedw_w-1 downto 0);
       smpl_buff_rdreq   : out std_logic;
-      smpl_buff_rddata  : in std_logic_vector(63 downto 0)
+      smpl_buff_rddata  : in std_logic_vector(63 downto 0);
+      pct_hdr_cap       : out std_logic
 
         );
 end data2packets_top;
@@ -76,6 +77,8 @@ signal smpl_buff_rdreq_reg          : std_logic;
 
 --input registers
 signal smpl_buff_rdusedw_reg        : std_logic_vector(smpl_buff_rdusedw_w-1 downto 0);
+
+signal pct_hdr_captured             : std_logic;
 
 begin
 
@@ -182,6 +185,19 @@ begin
    end if;
 end process;
 
+process(clk, reset_n)
+begin
+   if reset_n = '0' then 
+      pct_hdr_captured <= '0';
+   elsif (clk'event AND clk='1') then
+      if inst2_pct_state = "01" then 
+         pct_hdr_captured <= '1';
+      else 
+         pct_hdr_captured <= '0';
+      end if;
+   end if;
+end process;
+
 
 process(clk, reset_n)
 begin
@@ -280,6 +296,7 @@ end process;
 pct_buff_wrdata   <= pct_buff_wrdata_reg;  
 pct_buff_wrreq    <= smpl_buff_rdreq_reg;
 smpl_buff_rdreq   <= inst0_smpl_buff_rdreq;
+pct_hdr_cap       <= pct_hdr_captured;
 
 
 

src/rx_path_top/rx_path/synth/rx_path_top.vhd

@@ -41,6 +41,7 @@ entity rx_path_top is
       pct_fifo_wusedw      : in std_logic_vector(pct_buff_wrusedw_w-1 downto 0);
       pct_fifo_wrreq       : out std_logic;
       pct_fifo_wdata       : out std_logic_vector(63 downto 0);
+      pct_hdr_cap          : out std_logic;
       --sample nr
       clr_smpl_nr          : in std_logic;
       ld_smpl_nr           : in std_logic;
@@ -268,6 +269,7 @@ data2packets_top_inst2 : entity work.data2packets_top
       pct_buff_wrusedw  => pct_fifo_wusedw,
       pct_buff_wrreq    => pct_fifo_wrreq,
       pct_buff_wrdata   => pct_fifo_wdata,
+      pct_hdr_cap       => pct_hdr_cap,
       smpl_buff_rdusedw => inst1_rdusedw,
       smpl_buff_rdreq   => inst2_smpl_buff_rdreq,
       smpl_buff_rddata  => inst2_smpl_buff_rddata   

src/rxtx_top/synth/rxtx_top.vhd

@@ -139,6 +139,7 @@ signal inst1_DIQ_l               : std_logic_vector(TX_IQ_WIDTH downto 0);
 signal inst1_in_pct_full         : std_logic;
 signal inst1_pct_loss_flg        : std_logic;
 signal inst1_in_pct_rdy          : std_logic;
+signal inst1_in_pct_reset_n_req  : std_logic;
 
 --inst2
 signal inst2_wfm_infifo_wrusedw  : std_logic_vector(WFM_WFM_INFIFO_SIZE-1 downto 0);
@@ -154,6 +155,7 @@ signal inst3_diq_l               : std_logic_vector(TX_IQ_WIDTH downto 0);
 --inst5
 signal inst5_reset_n             : std_logic;
 signal inst5_smpl_nr_cnt         : std_logic_vector(63 downto 0);
+signal inst5_pct_hdr_cap         : std_logic;
 
 --inst6
 signal inst6_reset_n             : std_logic;
@@ -165,7 +167,7 @@ begin
    sync_reg0 : entity work.sync_reg 
    port map(tx_clk, from_fpgacfg.rx_en, '1', inst0_reset_n);
 
-   tx_in_pct_reset_n_req   <= inst0_reset_n;   
+   tx_in_pct_reset_n_req   <= inst0_reset_n AND inst1_in_pct_reset_n_req;   
    inst1_reset_n           <= inst0_reset_n;
    inst6_reset_n           <= inst0_reset_n;  
    inst5_reset_n           <= inst0_reset_n;
@@ -218,7 +220,7 @@ begin
       pct_sync_size        => from_fpgacfg.sync_size,
 
       pct_loss_flg         => inst1_pct_loss_flg,
-      pct_loss_flg_clr     => from_fpgacfg.txpct_loss_clr,
+      pct_loss_flg_clr     => inst5_pct_hdr_cap, --from_fpgacfg.txpct_loss_clr
 
       --txant
       txant_cyc_before_en  => from_fpgacfg.txant_pre,
@@ -238,7 +240,8 @@ begin
       fsync                => open, 
       DIQ_h                => inst1_DIQ_h,
       DIQ_l                => inst1_DIQ_l,
-      --fifo ports 
+      --fifo ports
+      in_pct_reset_n_req   => inst1_in_pct_reset_n_req,
       in_pct_rdreq         => tx_in_pct_rdreq,
       in_pct_data          => tx_in_pct_data,
       in_pct_rdy           => inst1_in_pct_rdy
@@ -395,6 +398,7 @@ begin
       pct_fifo_wusedw      => rx_pct_fifo_wusedw,
       pct_fifo_wrreq       => rx_pct_fifo_wrreq,
       pct_fifo_wdata       => rx_pct_fifo_wdata,
+      pct_hdr_cap          => inst5_pct_hdr_cap,
       --sample nr
       clr_smpl_nr          => from_fpgacfg.smpl_nr_clr,
       ld_smpl_nr           => '0',

src/tx_path_top/packets2data/synth/p2d_rd.vhd

@@ -301,9 +301,11 @@ begin
       pct_buff_rdreq(to_integer(crnt_buff_cnt))   <= rd_req_int;
    end process;
 
-   process(current_state, crnt_buff_cnt)
+   process(current_state, crnt_buff_cnt, reset_n)
    begin
-      if current_state = clr_buff then 
+      if reset_n = '0' then
+         pct_buff_clr_n <= (others=>'0');
+      elsif current_state = clr_buff then
          pct_buff_clr_n <= (others=>'1');
          pct_buff_clr_n(to_integer(crnt_buff_cnt))   <= '0';
       else