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Handle expression widths for EEE and NEE operators,
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 add named blocks and scope handling,
 add registers declared in named blocks.
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steve committed Jun 24, 1999
1 parent 33d4133 commit 11b2b17
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Showing 9 changed files with 234 additions and 84 deletions.
30 changes: 18 additions & 12 deletions Statement.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: Statement.cc,v 1.10 1999/06/19 21:06:16 steve Exp $"
#ident "$Id: Statement.cc,v 1.11 1999/06/24 04:24:18 steve Exp $"
#endif

# include "Statement.h"
Expand Down Expand Up @@ -56,24 +56,25 @@ PAssignNB::~PAssignNB()
{
}

PBlock::PBlock(BL_TYPE t, const list<Statement*>&st)
: bl_type_(t)
PBlock::PBlock(const string&n, BL_TYPE t, const svector<Statement*>&st)
: name_(n), bl_type_(t), list_(st)
{
nlist_ = st.size();
list_ = new Statement*[nlist_];
}

list<Statement*>::const_iterator s = st.begin();
for (unsigned idx = 0 ; s != st.end() ; s ++, idx += 1 ) {
list_[idx] = *s;
}
PBlock::PBlock(BL_TYPE t, const svector<Statement*>&st)
: bl_type_(t), list_(st)
{
}

PBlock::PBlock(BL_TYPE t)
: bl_type_(t)
{
}

PBlock::~PBlock()
{
for (unsigned idx = 0 ; idx < nlist_ ; idx += 1)
for (unsigned idx = 0 ; idx < list_.count() ; idx += 1)
delete list_[idx];

delete[]list_;
}

PCallTask::PCallTask(const string&n, const svector<PExpr*>&p)
Expand Down Expand Up @@ -136,6 +137,11 @@ PWhile::~PWhile()

/*
* $Log: Statement.cc,v $
* Revision 1.11 1999/06/24 04:24:18 steve
* Handle expression widths for EEE and NEE operators,
* add named blocks and scope handling,
* add registers declared in named blocks.
*
* Revision 1.10 1999/06/19 21:06:16 steve
* Elaborate and supprort to vvm the forever
* and repeat statements.
Expand Down
20 changes: 13 additions & 7 deletions Statement.h
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Original file line number Diff line number Diff line change
Expand Up @@ -19,11 +19,10 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: Statement.h,v 1.12 1999/06/19 21:06:16 steve Exp $"
#ident "$Id: Statement.h,v 1.13 1999/06/24 04:24:18 steve Exp $"
#endif

# include <string>
# include <list>
# include "svector.h"
# include "PExpr.h"
# include "LineInfo.h"
Expand Down Expand Up @@ -132,21 +131,23 @@ class PBlock : public Statement {
public:
enum BL_TYPE { BL_SEQ, BL_PAR };

explicit PBlock(BL_TYPE t, const list<Statement*>&st);
explicit PBlock(const string&n, BL_TYPE t, const svector<Statement*>&st);
explicit PBlock(BL_TYPE t, const svector<Statement*>&st);
explicit PBlock(BL_TYPE t);
~PBlock();

BL_TYPE bl_type() const { return bl_type_; }

unsigned size() const { return nlist_; }
const Statement*stat(unsigned idx) const { return list_[idx]; }
//unsigned size() const { return list_.count(); }
//const Statement*stat(unsigned idx) const { return list_[idx]; }

virtual void dump(ostream&out, unsigned ind) const;
virtual NetProc* elaborate(Design*des, const string&path) const;

private:
string name_;
const BL_TYPE bl_type_;
unsigned nlist_;
Statement**list_;
svector<Statement*>list_;
};

class PCallTask : public Statement {
Expand Down Expand Up @@ -326,6 +327,11 @@ class PWhile : public Statement {

/*
* $Log: Statement.h,v $
* Revision 1.13 1999/06/24 04:24:18 steve
* Handle expression widths for EEE and NEE operators,
* add named blocks and scope handling,
* add registers declared in named blocks.
*
* Revision 1.12 1999/06/19 21:06:16 steve
* Elaborate and supprort to vvm the forever
* and repeat statements.
Expand Down
44 changes: 29 additions & 15 deletions elaborate.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: elaborate.cc,v 1.47 1999/06/19 21:06:16 steve Exp $"
#ident "$Id: elaborate.cc,v 1.48 1999/06/24 04:24:18 steve Exp $"
#endif

/*
Expand Down Expand Up @@ -450,8 +450,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, const string&path) const
}

assert(sig);
NetNet*prt = des->find_signal(my_name + "." +
rmod->ports[idx]->name());
NetNet*prt = des->find_signal(my_name, rmod->ports[idx]->name());
assert(prt);

// Check that the parts have matching pin counts. If
Expand Down Expand Up @@ -739,7 +738,7 @@ NetNet* PEConcat::elaborate_net(Design*des, const string&path) const

NetNet* PEIdent::elaborate_net(Design*des, const string&path) const
{
NetNet*sig = des->find_signal(path+"."+text_);
NetNet*sig = des->find_signal(path, text_);
if (sig == 0) {
cerr << get_line() << ": Unable to find signal ``" <<
text_ << "''" << endl;
Expand Down Expand Up @@ -938,7 +937,7 @@ NetExpr*PEIdent::elaborate_expr(Design*des, const string&path) const

// If the identifier names a signal (a register or wire)
// then create a NetESignal node to handle it.
if (NetNet*net = des->find_signal(name)) {
if (NetNet*net = des->find_signal(path, text_)) {
NetESignal*node = des->get_esignal(net);
assert(idx_ == 0);
if (lsb_) {
Expand Down Expand Up @@ -1034,11 +1033,11 @@ NetNet* PAssign_::elaborate_lval(Design*des, const string&path,

/* Get the signal referenced by the identifier, and make sure
it is a register. */
NetNet*reg = des->find_signal(path+"."+id->name());
NetNet*reg = des->find_signal(path, id->name());

if (reg == 0) {
cerr << get_line() << ": Could not match signal: " <<
id->name() << endl;
cerr << get_line() << ": Could not match signal ``" <<
id->name() << "'' in ``" << path << "''" << endl;
return 0;
}
assert(reg);
Expand Down Expand Up @@ -1212,15 +1211,17 @@ NetProc* PBlock::elaborate(Design*des, const string&path) const
NetBlock*cur = new NetBlock(NetBlock::SEQU);
bool fail_flag = false;

string npath = name_.length()? (path+"."+name_) : path;

// Handle the special case that the block contains only one
// statement. There is no need to keep the block node.
if (size() == 1) {
NetProc*tmp = stat(0)->elaborate(des, path);
if (list_.count() == 1) {
NetProc*tmp = list_[0]->elaborate(des, npath);
return tmp;
}

for (unsigned idx = 0 ; idx < size() ; idx += 1) {
NetProc*tmp = stat(idx)->elaborate(des, path);
for (unsigned idx = 0 ; idx < list_.count() ; idx += 1) {
NetProc*tmp = list_[idx]->elaborate(des, npath);
if (tmp == 0) {
fail_flag = true;
continue;
Expand Down Expand Up @@ -1328,7 +1329,15 @@ NetProc* PCondit::elaborate(Design*des, const string&path) const
else
return new NetBlock(NetBlock::SEQU);
}


if (! expr->set_width(1)) {
cerr << get_line() << ": Unable to set expression width to 1."
<< endl;
des->errors += 1;
delete expr;
return 0;
}

// Well, I actually need to generate code to handle the
// conditional, so elaborate.
NetProc*i = if_->elaborate(des, path);
Expand Down Expand Up @@ -1447,7 +1456,7 @@ NetProc* PForStatement::elaborate(Design*des, const string&path) const
assert(id2);

NetBlock*top = new NetBlock(NetBlock::SEQU);
NetNet*sig = des->find_signal(path+"."+id1->name());
NetNet*sig = des->find_signal(path, id1->name());
if (sig == 0) {
cerr << id1->get_line() << ": register ``" << id1->name()
<< "'' unknown in this context." << endl;
Expand All @@ -1466,7 +1475,7 @@ NetProc* PForStatement::elaborate(Design*des, const string&path) const

body->append(statement_->elaborate(des, path));

sig = des->find_signal(path+"."+id2->name());
sig = des->find_signal(path, id2->name());
assert(sig);
NetAssign*step = new NetAssign("@for-assign", des, sig->pin_count(),
expr2_->elaborate_expr(des, path));
Expand Down Expand Up @@ -1629,6 +1638,11 @@ Design* elaborate(const map<string,Module*>&modules,

/*
* $Log: elaborate.cc,v $
* Revision 1.48 1999/06/24 04:24:18 steve
* Handle expression widths for EEE and NEE operators,
* add named blocks and scope handling,
* add registers declared in named blocks.
*
* Revision 1.47 1999/06/19 21:06:16 steve
* Elaborate and supprort to vvm the forever
* and repeat statements.
Expand Down
44 changes: 34 additions & 10 deletions netlist.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: netlist.cc,v 1.38 1999/06/19 21:06:16 steve Exp $"
#ident "$Id: netlist.cc,v 1.39 1999/06/24 04:24:18 steve Exp $"
#endif

# include <cassert>
Expand Down Expand Up @@ -425,6 +425,11 @@ void NetCase::set_case(unsigned idx, NetExpr*e, NetProc*p)
items_[idx].guard->set_width(expr_->expr_width());
}

NetCondit::NetCondit(NetExpr*ex, NetProc*i, NetProc*e)
: expr_(ex), if_(i), else_(e)
{
}

NetTask::~NetTask()
{
for (unsigned idx = 0 ; idx < nparms_ ; idx += 1)
Expand Down Expand Up @@ -468,8 +473,10 @@ bool NetEBinary::set_width(unsigned w)
/* Comparison operators allow the subexpressions to have
their own natural width. However, I do need to make
sure that the subexpressions have the same width. */
case 'e': /* == */
case 'n': /* != */
case 'E': /* === */
case 'e': /* == */
case 'N': /* !== */
case 'n': /* != */
case '<': /* < */
case '>': /* > */
assert(w == 1);
Expand Down Expand Up @@ -1091,18 +1098,30 @@ void Design::del_signal(NetNet*net)
net->design_ = 0;
}

NetNet* Design::find_signal(const string&name)
/*
* This method looks for a string given a current context as a
* starting point.
*/
NetNet* Design::find_signal(const string&path, const string&name)
{
if (signals_ == 0)
return 0;

NetNet*cur = signals_;
do {
if (cur->name() == name)
return cur;
string root = path;
while (root.size() > 0) {

cur = cur->sig_prev_;
} while (cur != signals_);
string fulname = root + "." + name;
NetNet*cur = signals_;
do {
if (cur->name() == fulname)
return cur;

cur = cur->sig_prev_;
} while (cur != signals_);

unsigned pos = root.rfind('.');
root = root.substr(0, pos);
}

return 0;
}
Expand Down Expand Up @@ -1228,6 +1247,11 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*))

/*
* $Log: netlist.cc,v $
* Revision 1.39 1999/06/24 04:24:18 steve
* Handle expression widths for EEE and NEE operators,
* add named blocks and scope handling,
* add registers declared in named blocks.
*
* Revision 1.38 1999/06/19 21:06:16 steve
* Elaborate and supprort to vvm the forever
* and repeat statements.
Expand Down
12 changes: 8 additions & 4 deletions netlist.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: netlist.h,v 1.41 1999/06/19 21:06:16 steve Exp $"
#ident "$Id: netlist.h,v 1.42 1999/06/24 04:24:18 steve Exp $"
#endif

/*
Expand Down Expand Up @@ -712,8 +712,7 @@ class NetCase : public NetProc {
class NetCondit : public NetProc {

public:
NetCondit(NetExpr*ex, NetProc*i, NetProc*e)
: expr_(ex), if_(i), else_(e) { }
explicit NetCondit(NetExpr*ex, NetProc*i, NetProc*e);

const NetExpr*expr() const { return expr_; }
void emit_recurse_if(ostream&, struct target_t*) const;
Expand Down Expand Up @@ -1188,7 +1187,7 @@ class Design {
// SIGNALS
void add_signal(NetNet*);
void del_signal(NetNet*);
NetNet*find_signal(const string&name);
NetNet*find_signal(const string&path, const string&name);

// Memories
void add_memory(NetMemory*);
Expand Down Expand Up @@ -1291,6 +1290,11 @@ extern ostream& operator << (ostream&, NetNet::Type);

/*
* $Log: netlist.h,v $
* Revision 1.42 1999/06/24 04:24:18 steve
* Handle expression widths for EEE and NEE operators,
* add named blocks and scope handling,
* add registers declared in named blocks.
*
* Revision 1.41 1999/06/19 21:06:16 steve
* Elaborate and supprort to vvm the forever
* and repeat statements.
Expand Down
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