Add memories to the parse and elaboration phases.

PExpr.h

@@ -19,11 +19,12 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: PExpr.h,v 1.4 1998/11/11 00:01:51 steve Exp $"
+#ident "$Id: PExpr.h,v 1.5 1999/04/19 01:59:36 steve Exp $"
 #endif
 
 # include  <string>
 # include  "verinum.h"
+# include  "LineInfo.h"
 
 class Design;
 class NetNet;
@@ -38,7 +39,7 @@ class NetExpr;
  * up a netlist interpretation of the expression.
  */
 
-class PExpr {
+class PExpr : public LineInfo {
     public:
       virtual ~PExpr();
 
@@ -63,7 +64,7 @@ class PEIdent : public PExpr {
 
     public:
       explicit PEIdent(const string&s)
-      : text_(s), msb_(0), lsb_(0) { }
+      : text_(s), msb_(0), lsb_(0), idx_(0) { }
 
       virtual void dump(ostream&) const;
       virtual NetNet* elaborate_net(Design*des, const string&path) const;
@@ -77,6 +78,10 @@ class PEIdent : public PExpr {
 	// Use these to support bit- and part-select operators.
       PExpr*msb_;
       PExpr*lsb_;
+
+	// If this is a reference to a memory, this is the index
+	// expression.
+      PExpr*idx_;
 };
 
 class PENumber : public PExpr {
@@ -146,6 +151,9 @@ class PEBinary : public PExpr {
 
 /*
  * $Log: PExpr.h,v $
+ * Revision 1.5  1999/04/19 01:59:36  steve
+ *  Add memories to the parse and elaboration phases.
+ *
  * Revision 1.4  1998/11/11 00:01:51  steve
  *  Check net ranges in declarations.
  *

PWire.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: PWire.h,v 1.2 1998/11/23 00:20:22 steve Exp $"
+#ident "$Id: PWire.h,v 1.3 1999/04/19 01:59:36 steve Exp $"
 #endif
 
 # include  "netlist.h"
@@ -37,7 +37,8 @@ class PWire {
 
     public:
       PWire(const string&n, NetNet::Type t =NetNet::IMPLICIT)
-      : name(n), type(t), port_type(NetNet::NOT_A_PORT), msb(0), lsb(0)
+      : name(n), type(t), port_type(NetNet::NOT_A_PORT), msb(0),
+	lsb(0), lidx(0), ridx(0)
       { }
 
       string name;
@@ -47,6 +48,11 @@ class PWire {
       PExpr*msb;
       PExpr*lsb;
 
+	// If this wire is actually a memory, these indices will give
+	// me the size and address range of the memory.
+      PExpr*lidx;
+      PExpr*ridx;
+
       map<string,string> attributes;
 
 	// Write myself to the specified stream.
@@ -61,6 +67,9 @@ class PWire {
 
 /*
  * $Log: PWire.h,v $
+ * Revision 1.3  1999/04/19 01:59:36  steve
+ *  Add memories to the parse and elaboration phases.
+ *
  * Revision 1.2  1998/11/23 00:20:22  steve
  *  NetAssign handles lvalues as pin links
  *  instead of a signal pointer,

design_dump.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: design_dump.cc,v 1.16 1999/03/15 02:43:32 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.17 1999/04/19 01:59:36 steve Exp $"
 #endif
 
 /*
@@ -57,6 +57,12 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
       dump_obj_attr(o, ind+4);
 }
 
+void NetMemory::dump(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << ""  << name_ << "[" << width_ << "] " <<
+	    "[" << idxh_ << ":" << idxl_ << "]" << endl;
+}
+
 
 /* Dump a NetNode and its pins. Dump what I know about the netnode on
    the first line, then list all the pins, with the name of the
@@ -463,6 +469,13 @@ void NetESignal::dump(ostream&o) const
       o << name();
 }
 
+void NetEMemory::dump(ostream&o) const
+{
+      o << mem_->name() << "[";
+      idx_->dump(o);
+      o << "]";
+}
+
 void NetESignal::dump_node(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "" << "Expression Node: " << name() << endl;
@@ -500,6 +513,15 @@ void Design::dump(ostream&o) const
 	    } while (cur != signals_->sig_next_);
       }
 
+      o << "ELABORATED MEMORIES:" << endl;
+      {
+	    map<string,NetMemory*>::const_iterator pp;
+	    for (pp = memories_.begin()
+		       ; pp != memories_.end() ; pp ++) {
+		  (*pp).second->dump(o, 0);
+	    }
+      }
+
       o << "ELABORATED NODES:" << endl;
 
 	// dump the nodes,
@@ -521,6 +543,9 @@ void Design::dump(ostream&o) const
 
 /*
  * $Log: design_dump.cc,v $
+ * Revision 1.17  1999/04/19 01:59:36  steve
+ *  Add memories to the parse and elaboration phases.
+ *
  * Revision 1.16  1999/03/15 02:43:32  steve
  *  Support more operators, especially logical.
  *

elaborate.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: elaborate.cc,v 1.18 1999/03/15 02:43:32 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.19 1999/04/19 01:59:36 steve Exp $"
 #endif
 
 /*
@@ -91,7 +91,13 @@ static void do_assign(Design*des, const string&path,
 static const map<string,Module*>* modlist = 0;
 static const map<string,PUdp*>*   udplist = 0;
 
-/* Elaborate a source wire. Generally pretty easy. */
+/*
+ * Elaborate a source wire. The "wire" is the declaration of wires,
+ * registers, ports and memories. The parser has already merged the
+ * multiple properties of a wire (i.e. "input wire") so come the
+ * elaboration this creates an object in the design that represent the
+ * defined item.
+ */
 void PWire::elaborate(Design*des, const string&path) const
 {
       NetNet::Type wtype = type;
@@ -100,6 +106,8 @@ void PWire::elaborate(Design*des, const string&path) const
 
       unsigned wid = 1;
 
+	/* Wires, registers and memories can have a width, expressed
+	   as the msb index and lsb index. */
       if (msb && lsb) {
 	    verinum*mval = msb->eval_const();
 	    assert(mval);
@@ -123,10 +131,29 @@ void PWire::elaborate(Design*des, const string&path) const
 	    wid = val->as_ulong();
       }
 
-      NetNet*sig = new NetNet(path + "." + name, wtype, wid);
-      sig->port_type(port_type);
-      sig->set_attributes(attributes);
-      des->add_signal(sig);
+      if (lidx || ridx) {
+	      // If the register has indices, then this is a
+	      // memory. Create the memory object.
+	    verinum*lval = lidx->eval_const();
+	    assert(lval);
+	    verinum*rval = ridx->eval_const();
+	    assert(rval);
+
+	    long lnum = lval->as_long();
+	    long rnum = rval->as_long();
+	    delete lval;
+	    delete rval;
+	    NetMemory*sig = new NetMemory(path+"."+name, wid, lnum, rnum);
+	    sig->set_attributes(attributes);
+	    des->add_memory(sig);
+
+      } else {
+
+	    NetNet*sig = new NetNet(path + "." + name, wtype, wid);
+	    sig->port_type(port_type);
+	    sig->set_attributes(attributes);
+	    des->add_signal(sig);
+      }
 }
 
 void PGate::elaborate(Design*des, const string&path) const
@@ -667,7 +694,26 @@ NetExpr*PEIdent::elaborate_expr(Design*des, const string&path) const
 		  return node;
 	    }
 
-	    assert(0);
+	    if (NetMemory*mem = des->find_memory(name)) {
+		  assert(msb_ != 0);
+		  assert(lsb_ == 0);
+		  assert(idx_ == 0);
+		  NetExpr*i = msb_->elaborate_expr(des, path);
+		  if (i == 0) {
+			cerr << get_line() << ": Unable to exaborate "
+			      "index expression `" << *msb_ << "'" << endl;
+			des->errors += 1;
+			return 0;
+		  }
+
+		  NetEMemory*node = new NetEMemory(mem, i);
+		  return node;
+	    }
+
+	    cerr << get_line() << ": Unable to bind wire/reg/memory "
+		  "`" << path << "." << text_ << "'" << endl;
+	    des->errors += 1;
+	    return 0;
       }
 }
 
@@ -709,6 +755,11 @@ NetProc* PAssign::elaborate(Design*des, const string&path) const
       assert(expr_);
 
       NetExpr*rval = expr_->elaborate_expr(des, path);
+      if (rval == 0) {
+	    cerr << get_line() << ": " << "failed to elaborate expression."
+		 << endl;
+	    return 0;
+      }
       assert(rval);
 
       NetAssign*cur = new NetAssign(reg, rval);
@@ -977,6 +1028,9 @@ Design* elaborate(const map<string,Module*>&modules,
 
 /*
  * $Log: elaborate.cc,v $
+ * Revision 1.19  1999/04/19 01:59:36  steve
+ *  Add memories to the parse and elaboration phases.
+ *
  * Revision 1.18  1999/03/15 02:43:32  steve
  *  Support more operators, especially logical.
  *

emit.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: emit.cc,v 1.6 1999/02/08 02:49:56 steve Exp $"
+#ident "$Id: emit.cc,v 1.7 1999/04/19 01:59:36 steve Exp $"
 #endif
 
 /*
@@ -173,6 +173,15 @@ void Design::emit(ostream&o, struct target_t*tgt) const
       }
 
 
+	// emit memories
+      {
+	    map<string,NetMemory*>::const_iterator mi;
+	    for (mi = memories_.begin() ;  mi != memories_.end() ; mi++) {
+		  tgt->memory(o, (*mi).second);
+	    }
+      }
+
+
 	// emit nodes
       {
 	    NetNode*cur = nodes_->node_next_;
@@ -205,6 +214,11 @@ void NetEIdent::expr_scan(struct expr_scan_t*tgt) const
       tgt->expr_ident(this);
 }
 
+void NetEMemory::expr_scan(struct expr_scan_t*tgt) const
+{
+      tgt->expr_memory(this);
+}
+
 void NetESignal::expr_scan(struct expr_scan_t*tgt) const
 {
       tgt->expr_signal(this);
@@ -234,6 +248,9 @@ void emit(ostream&o, const Design*des, const char*type)
 
 /*
  * $Log: emit.cc,v $
+ * Revision 1.7  1999/04/19 01:59:36  steve
+ *  Add memories to the parse and elaboration phases.
+ *
  * Revision 1.6  1999/02/08 02:49:56  steve
  *  Turn the NetESignal into a NetNode so
  *  that it can connect to the netlist.