Makefile patches to support target loading under cygwin.

Makefile.in

@@ -18,7 +18,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.73 2000/10/08 22:36:55 steve Exp $"
+#ident "$Id: Makefile.in,v 1.74 2000/10/15 21:02:08 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -110,8 +110,18 @@ verilog: $(srcdir)/verilog.sh
 	    -e 's;@dllib@;@DLLIB@;' \
 	    -e 's;@$(tmp4)@;@CXX@;' < $< > $@
 
+ifeq (@CYGWIN@,yes)
+ivl@EXEEXT@: $O ivl.def
+	dlltool --dllname ivl@EXEEXT@ --def ivl.def \
+		--output-lib libivl.a --output-exp ivl.exp
+#	$(CXX) -o ivl@EXEEXT@ -Wl,--base-file,ivl.base ivl.exp $O $(dllib)
+#	dlltool --dllname ivl@EXEEXT@ --base-file ivl.base \
+#		--output-exp ivl.exp --def ivl.def
+	$(CXX) -o ivl@EXEEXT@ ivl.exp $O $(dllib)	
+else
 ivl@EXEEXT@: $O
-	$(CXX) $(CXXFLAGS) $(rdynamic) -o ivl@EXEEXT@ $O $(dllib)
+	$(CXX) $(CXXFLAGS) $(rdynamic) $(LDFLAGS) -o ivl@EXEEXT@ $O $(dllib)
+endif
 
 
 %.o: %.cc

ivl.def

@@ -0,0 +1,62 @@
+EXPORTS
+
+ivl_design_flag
+ivl_design_process
+ivl_design_root
+
+ivl_const_bits
+ivl_const_pin
+ivl_const_pins
+ivl_const_signed
+
+ivl_expr_type
+ivl_expr_bits
+ivl_expr_name
+ivl_expr_opcode
+ivl_expr_oper1
+ivl_expr_oper2
+ivl_expr_oper3
+ivl_expr_signed
+ivl_expr_string
+ivl_expr_width
+
+ivl_logic_name
+ivl_logic_basename
+ivl_logic_type
+ivl_logic_pin
+ivl_logic_pins
+
+ivl_nexus_name
+ivl_nexus_ptrs
+ivl_nexus_ptr
+
+ivl_scope_children
+ivl_scope_logs
+ivl_scope_log
+ivl_scope_name
+ivl_scope_sigs
+ivl_scope_sig
+
+ivl_signal_pins
+ivl_signal_port
+ivl_signal_type
+ivl_signal_name
+ivl_signal_basename
+
+ivl_process_type
+ivl_process_stmt
+
+ivl_statement_type
+
+ivl_stmt_block_count
+ivl_stmt_blocl_stmt
+ivl_stmt_cond_expr
+ivl_stmt_cond_false
+ivl_stmt_cond_true
+ivl_stmt_delay_val
+ivl_stmt_lwidth
+ivl_stmt_name
+ivl_stmt_parm
+ivl_stmt_parm_count
+ivl_stmt_rval
+ivl_stmt_sub_stmt

tgt-stub/Makefile.in

@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.3 2000/10/04 17:08:31 steve Exp $"
+#ident "$Id: Makefile.in,v 1.4 2000/10/15 21:02:08 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -39,7 +39,7 @@ INSTALL = @INSTALL@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_DATA = @INSTALL_DATA@
 
-CPPFLAGS = @CPPFLAGS@ @DEFS@ -fpic
+CPPFLAGS = @CPPFLAGS@ @DEFS@ @PICFLAG@
 CXXFLAGS = @CXXFLAGS@
 LDFLAGS = @LDFLAGS@
 
@@ -52,8 +52,17 @@ all: stub.tgt
 
 O = stub.o
 
-stub.tgt: $O
-	$(CC) -shared -o $@ $O
+ifeq (@CYGWIN@,yes)
+  TGTLDFLAGS=-Wl,--enable-auto-image-base -L.. -livl
+  TGTDEPLIBS=../libivl.a
+else
+  TGTLDFLAGS=
+  TGTDEPLIBS=
+endif
+
+
+stub.tgt: $O $(TGTDEPLIBS)
+	$(CC) -shared -o $@ $O $(TGTLDFLAGS)
 
 clean:
 	rm -f *.o dep/*.d

tgt-stub/stub.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: stub.c,v 1.17 2000/10/15 04:46:23 steve Exp $"
+#ident "$Id: stub.c,v 1.18 2000/10/15 21:02:08 steve Exp $"
 #endif
 
 /*
@@ -168,6 +168,7 @@ static int show_process(ivl_process_t net)
       return 0;
 }
 
+
 static void show_signal(ivl_signal_t net)
 {
       const char*type = "?";
@@ -315,9 +316,16 @@ int target_net_probe(const char*name, ivl_net_probe_t net)
       return 0;
 }
 
+#ifdef __CYGWIN32__
+#include <cygwin/cygwin_dll.h>
+DECLARE_CYGWIN_DLL(DllMain);
+#endif
 
 /*
  * $Log: stub.c,v $
+ * Revision 1.18  2000/10/15 21:02:08  steve
+ *  Makefile patches to support target loading under cygwin.
+ *
  * Revision 1.17  2000/10/15 04:46:23  steve
  *  Scopes and processes are accessible randomly from
  *  the design, and signals and logic are accessible

tgt-verilog/Makefile.in

@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.2 2000/10/04 17:08:31 steve Exp $"
+#ident "$Id: Makefile.in,v 1.3 2000/10/15 21:02:08 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -39,7 +39,7 @@ INSTALL = @INSTALL@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_DATA = @INSTALL_DATA@
 
-CPPFLAGS = @CPPFLAGS@ @DEFS@ -fpic
+CPPFLAGS = @CPPFLAGS@ @DEFS@ @PICFLAG@
 CXXFLAGS = @CXXFLAGS@
 LDFLAGS = @LDFLAGS@
 
@@ -52,8 +52,16 @@ all: verilog.tgt
 
 O = verilog.o
 
-verilog.tgt: $O
-	$(CC) -shared -o $@ $O
+ifeq (@CYGWIN@,yes)
+  TGTLDFLAGS=-Wl,--enable-auto-image-base -L.. -livl
+  TGTDEPLIBS=../libivl.a
+else
+  TGTLDFLAGS=
+  TGTDEPLIBS=
+endif
+
+verilog.tgt: $O $(TGTDEPLIBS)
+	$(CC) -shared -o $@ $O $(TGTLDFLAGS)
 
 clean:
 	rm -f *.o dep/*.d

tgt-verilog/verilog.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: verilog.c,v 1.11 2000/10/15 04:46:23 steve Exp $"
+#ident "$Id: verilog.c,v 1.12 2000/10/15 21:02:09 steve Exp $"
 #endif
 
 /*
@@ -286,8 +286,16 @@ int target_net_signal(const char*name, ivl_signal_t net)
       return 0;
 }
 
+#ifdef __CYGWIN32__
+#include <cygwin/cygwin_dll.h>
+DECLARE_CYGWIN_DLL(DllMain);
+#endif
+
 /*
  * $Log: verilog.c,v $
+ * Revision 1.12  2000/10/15 21:02:09  steve
+ *  Makefile patches to support target loading under cygwin.
+ *
  * Revision 1.11  2000/10/15 04:46:23  steve
  *  Scopes and processes are accessible randomly from
  *  the design, and signals and logic are accessible